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Searched refs:clk_id (Results 1 – 7 of 7) sorted by relevance

/trusted-firmware-a/plat/ti/k3/common/drivers/ti_sci/
A Dti_sci.h115 int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id,
118 int ti_sci_clock_idle(uint32_t dev_id, uint8_t clk_id);
119 int ti_sci_clock_put(uint32_t dev_id, uint8_t clk_id);
120 int ti_sci_clock_is_auto(uint32_t dev_id, uint8_t clk_id,
122 int ti_sci_clock_is_on(uint32_t dev_id, uint8_t clk_id,
124 int ti_sci_clock_is_off(uint32_t dev_id, uint8_t clk_id,
126 int ti_sci_clock_set_parent(uint32_t dev_id, uint8_t clk_id,
128 int ti_sci_clock_get_parent(uint32_t dev_id, uint8_t clk_id,
130 int ti_sci_clock_get_num_parents(uint32_t dev_id, uint8_t clk_id,
132 int ti_sci_clock_get_match_freq(uint32_t dev_id, uint8_t clk_id,
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A Dti_sci.c652 req.clk_id = clk_id; in ti_sci_clock_set_state()
699 req.clk_id = clk_id; in ti_sci_clock_get_state()
728 int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_get() argument
756 return ti_sci_clock_set_state(dev_id, clk_id, 0, in ti_sci_clock_idle()
774 return ti_sci_clock_set_state(dev_id, clk_id, 0, in ti_sci_clock_put()
901 req.clk_id = clk_id; in ti_sci_clock_set_parent()
942 req.clk_id = clk_id; in ti_sci_clock_get_parent()
985 req.clk_id = clk_id; in ti_sci_clock_get_num_parents()
1037 req.clk_id = clk_id; in ti_sci_clock_get_match_freq()
1089 req.clk_id = clk_id; in ti_sci_clock_set_freq()
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A Dti_sci_protocol.h242 uint8_t clk_id; member
263 uint8_t clk_id; member
301 uint8_t clk_id; member
318 uint8_t clk_id; member
349 uint8_t clk_id; member
392 uint8_t clk_id; member
448 uint8_t clk_id; member
466 uint8_t clk_id; member
/trusted-firmware-a/plat/xilinx/versal/pm_service/
A Dpm_api_sys.h54 enum pm_ret_status pm_clock_enable(uint32_t clk_id, uint32_t flag);
55 enum pm_ret_status pm_clock_disable(uint32_t clk_id, uint32_t flag);
56 enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state,
58 enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider,
62 enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent,
64 enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent,
66 enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate,
68 enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
70 enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
72 enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode,
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A Dpm_api_sys.c520 clk_id); in pm_clock_enable()
539 clk_id); in pm_clock_disable()
560 clk_id); in pm_clock_get_state()
581 clk_id, divider); in pm_clock_set_divider()
602 clk_id); in pm_clock_get_divider()
623 clk_id, parent); in pm_clock_set_parent()
644 clk_id); in pm_clock_get_parent()
664 clk_id); in pm_clock_get_rate()
708 clk_id, param); in pm_pll_get_param()
729 clk_id, mode); in pm_pll_set_mode()
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/trusted-firmware-a/plat/nvidia/tegra/drivers/bpmp_ipc/
A Dintf.c301 int tegra_bpmp_ipc_enable_clock(uint32_t clk_id) in tegra_bpmp_ipc_enable_clock() argument
307 if (clk_id != TEGRA_CLK_SE) { in tegra_bpmp_ipc_enable_clock()
312 req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_ENABLE, clk_id); in tegra_bpmp_ipc_enable_clock()
318 clk_id, ret); in tegra_bpmp_ipc_enable_clock()
324 int tegra_bpmp_ipc_disable_clock(uint32_t clk_id) in tegra_bpmp_ipc_disable_clock() argument
330 if (clk_id != TEGRA_CLK_SE) { in tegra_bpmp_ipc_disable_clock()
335 req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_DISABLE, clk_id); in tegra_bpmp_ipc_disable_clock()
341 clk_id, ret); in tegra_bpmp_ipc_disable_clock()
/trusted-firmware-a/plat/nvidia/tegra/include/drivers/
A Dbpmp_ipc.h35 int tegra_bpmp_ipc_enable_clock(uint32_t clk_id);
41 int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);

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