| /trusted-firmware-a/plat/layerscape/board/ls1043/ |
| A D | ls1043_psci.c | 56 static void ls1043_reset_core(int core_pos) in ls1043_reset_core() argument
58 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); in ls1043_reset_core()
61 mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_0_OFFSET + core_pos * 8, in ls1043_reset_core()
63 mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_1_OFFSET + core_pos * 8, in ls1043_reset_core()
74 core_pos * 4, htobe32(1U << 31)); in ls1043_reset_core()
98 int core_pos = plat_core_pos_by_mpidr(mpidr); in ls1043_pwr_domain_on() local
101 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); in ls1043_pwr_domain_on()
102 core_mask = 1 << core_pos; in ls1043_pwr_domain_on()
116 ls1043_reset_core(core_pos); in ls1043_pwr_domain_on()
|
| /trusted-firmware-a/plat/arm/board/arm_fpga/ |
| A D | fpga_topology.c | 56 unsigned int core_pos; in plat_core_pos_by_mpidr() local
69 core_pos = plat_fpga_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
72 if (fpga_valid_mpids[core_pos] != VALID_MPID) { in plat_core_pos_by_mpidr()
76 return core_pos; in plat_core_pos_by_mpidr()
|
| /trusted-firmware-a/lib/fconf/ |
| A D | fconf_mpmm_getter.c | 31 int core_pos; in fconf_populate_mpmm_cpu() local
34 core_pos = plat_core_pos_by_mpidr(mpidr); in fconf_populate_mpmm_cpu()
35 if (core_pos < 0) { in fconf_populate_mpmm_cpu()
39 core = &fconf_mpmm_topology.cores[core_pos]; in fconf_populate_mpmm_cpu()
|
| /trusted-firmware-a/lib/extensions/amu/aarch32/ |
| A D | amu.c | 201 unsigned int core_pos = plat_my_core_pos(); in amu_enable() local
203 amcntenset1_el0_px = topology->cores[core_pos].enable; in amu_enable()
290 unsigned int core_pos; in amu_context_save() local
306 core_pos = plat_my_core_pos(); in amu_context_save()
307 ctx = &amu_ctxs_[core_pos]; in amu_context_save()
353 unsigned int core_pos; in amu_context_restore() local
370 core_pos = plat_my_core_pos(); in amu_context_restore()
371 ctx = &amu_ctxs_[core_pos]; in amu_context_restore()
|
| /trusted-firmware-a/plat/arm/board/fvp/ |
| A D | fvp_gicv3.c | 75 unsigned int core_pos = plat_my_core_pos(); in fvp_gicv3_make_rdistrif_rw() local
78 if (fvp_gicr_rw_region_init[core_pos] != true) { in fvp_gicv3_make_rdistrif_rw()
80 (core_pos * BASE_GICR_SIZE), in fvp_gicv3_make_rdistrif_rw()
91 fvp_gicr_rw_region_init[core_pos] = true; in fvp_gicv3_make_rdistrif_rw()
|
| /trusted-firmware-a/plat/socionext/synquacer/drivers/scp/ |
| A D | sq_scmi.c | 138 int lvl = 0, ret, core_pos; in sq_scmi_on() local
147 core_pos = plat_core_pos_by_mpidr(mpidr); in sq_scmi_on()
148 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); in sq_scmi_on()
151 sq_core_pos_to_scmi_dmn_id_map[core_pos], in sq_scmi_on()
|
| /trusted-firmware-a/lib/extensions/amu/aarch64/ |
| A D | amu.c | 257 unsigned int core_pos = plat_my_core_pos(); in amu_enable() local
259 amcntenset1_el0_px = topology->cores[core_pos].enable; in amu_enable()
443 unsigned int core_pos; in amu_context_save() local
461 core_pos = plat_my_core_pos(); in amu_context_save()
462 ctx = &amu_ctxs_[core_pos]; in amu_context_save()
535 unsigned int core_pos; in amu_context_restore() local
555 core_pos = plat_my_core_pos(); in amu_context_restore()
556 ctx = &amu_ctxs_[core_pos]; in amu_context_restore()
|
| /trusted-firmware-a/lib/mpmm/ |
| A D | mpmm.c | 54 unsigned int core_pos = plat_my_core_pos(); in mpmm_supported() local
56 supported = topology->cores[core_pos].supported && in mpmm_supported()
|
| /trusted-firmware-a/drivers/arm/css/scp/ |
| A D | css_pm_scmi.c | 93 static void css_scp_core_pos_to_scmi_channel(unsigned int core_pos, in css_scp_core_pos_to_scmi_channel() argument
98 composite_id = plat_css_core_pos_to_scmi_dmn_id_map[core_pos]; in css_scp_core_pos_to_scmi_channel()
217 unsigned int lvl = 0, channel_id, core_pos, domain_id; in css_scp_on() local
227 core_pos = (unsigned int)plat_core_pos_by_mpidr(mpidr); in css_scp_on()
228 assert(core_pos < PLATFORM_CORE_COUNT); in css_scp_on()
230 css_scp_core_pos_to_scmi_channel(core_pos, &domain_id, in css_scp_on()
|
| /trusted-firmware-a/plat/qti/common/src/ |
| A D | qti_pm.c | 134 int core_pos = plat_core_pos_by_mpidr(mpidr); in qti_cpu_power_on() local
137 if (core_pos < 0 || core_pos >= QTISECLIB_PLAT_CORE_COUNT) { in qti_cpu_power_on()
|
| /trusted-firmware-a/plat/nxp/common/psci/ |
| A D | plat_psci.c | 36 int core_pos = plat_core_pos(mpidr); in _pwr_domain_on() local
40 if (core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT) { in _pwr_domain_on()
47 core_mask = (1 << core_pos); in _pwr_domain_on()
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
| A D | plat_psci_handlers.c | 209 uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; in tegra_get_afflvl1_pwr_state() local
210 plat_local_state_t target = states[core_pos]; in tegra_get_afflvl1_pwr_state()
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t186/ |
| A D | plat_psci_handlers.c | 200 uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; in tegra_get_afflvl1_pwr_state() local
203 plat_local_state_t target = states[core_pos]; in tegra_get_afflvl1_pwr_state()
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t210/ |
| A D | plat_psci_handlers.c | 107 int core_pos = read_mpidr() & MPIDR_CPU_MASK; in tegra_soc_get_target_pwr_state() local
113 target = *(states + core_pos); in tegra_soc_get_target_pwr_state()
|