| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/fconf/ |
| A D | amu-bindings.rst.txt | 31 The ``amus`` node describes the |AMUs| implemented by the cores in the system.
38 registers of one or more |AMUs|, and may be shared by multiple cores.
73 An example system offering four cores made up of two clusters, where the cores
137 In this situation, ``cpu0`` and ``cpu1`` (the two cores in the first cluster),
139 ``cpu3`` (the two cores in the second cluster), share the view of their |AMUs|
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| A D | mpmm-bindings.rst.txt | 30 An example system offering two cores, one with support for |MPMM| and one
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| /trusted-firmware-a/docs/components/fconf/ |
| A D | amu-bindings.rst | 31 The ``amus`` node describes the |AMUs| implemented by the cores in the system.
38 registers of one or more |AMUs|, and may be shared by multiple cores.
73 An example system offering four cores made up of two clusters, where the cores
137 In this situation, ``cpu0`` and ``cpu1`` (the two cores in the first cluster),
139 ``cpu3`` (the two cores in the second cluster), share the view of their |AMUs|
|
| A D | mpmm-bindings.rst | 30 An example system offering two cores, one with support for |MPMM| and one
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| /trusted-firmware-a/docs/plat/ |
| A D | nvidia-tegra.rst | 7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
13 eight cores if required.
22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
30 heterogeneous multi-processing with all six cores if required.
33 fully Armv8-A architecture compatible. Each of the two Denver cores
37 cache, which services both cores.
60 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
61 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
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| A D | mt8183.rst | 5 The chip incorporates eight cores - four Cortex-A53 little cores and Cortex-A73.
|
| A D | mt8195.rst | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
|
| A D | mt8192.rst | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
|
| A D | rpi3.rst | 5 Arm Cortex-A53 cores.
25 card) and is located between all Arm cores and the DRAM. Check the `Raspberry Pi
30 the cores boot in AArch64 mode.
40 the cores are powered on at the same time and start at address **0x0**.
48 Ideally, we want to load the kernel and have all cores available, which means
49 that we need to make the secondary cores work in the way the kernel expects, as
50 explained in `Secondary cores`_. In practice, a small bootstrap is needed
89 All addresses are Physical Addresses from the point of view of the Arm cores.
162 Secondary cores
178 cold boot, all secondary cores wait in a loop until they are given given an
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | nvidia-tegra.rst.txt | 7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
13 eight cores if required.
22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
30 heterogeneous multi-processing with all six cores if required.
33 fully Armv8-A architecture compatible. Each of the two Denver cores
37 cache, which services both cores.
60 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
61 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
|
| A D | mt8183.rst.txt | 5 The chip incorporates eight cores - four Cortex-A53 little cores and Cortex-A73.
|
| A D | mt8192.rst.txt | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
|
| A D | mt8195.rst.txt | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
|
| A D | rpi3.rst.txt | 5 Arm Cortex-A53 cores.
25 card) and is located between all Arm cores and the DRAM. Check the `Raspberry Pi
30 the cores boot in AArch64 mode.
40 the cores are powered on at the same time and start at address **0x0**.
48 Ideally, we want to load the kernel and have all cores available, which means
49 that we need to make the secondary cores work in the way the kernel expects, as
50 explained in `Secondary cores`_. In practice, a small bootstrap is needed
89 All addresses are Physical Addresses from the point of view of the Arm cores.
162 Secondary cores
178 cold boot, all secondary cores wait in a loop until they are given given an
[all …]
|
| A D | brcm-stingray.rst.txt | 6 Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | mpmm.rst.txt | 5 some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
6 Cortex-A510 cores. This mechanism detects and limits high-activity events to
26 limiting the number of cores that can execute higher-activity workloads or
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| /trusted-firmware-a/docs/components/ |
| A D | mpmm.rst | 5 some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
6 Cortex-A510 cores. This mechanism detects and limits high-activity events to
26 limiting the number of cores that can execute higher-activity workloads or
|
| /trusted-firmware-a/fdts/ |
| A D | arm_fpga.dts | 6 * Number and kind of CPU cores differs from image to image, so the
54 /* This node will be removed at runtime on cores without SPE. */
97 /* The GICR size will be adjusted at runtime to match the cores. */
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| /trusted-firmware-a/include/lib/mpmm/ |
| A D | mpmm.h | 46 struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ member
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| /trusted-firmware-a/include/lib/extensions/ |
| A D | amu.h | 35 struct amu_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ member
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| /trusted-firmware-a/lib/mpmm/ |
| A D | mpmm.c | 56 supported = topology->cores[core_pos].supported && in mpmm_supported()
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| /trusted-firmware-a/lib/fconf/ |
| A D | fconf_mpmm_getter.c | 39 core = &fconf_mpmm_topology.cores[core_pos]; in fconf_populate_mpmm_cpu()
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| A D | fconf_amu_getter.c | 100 amu = &fconf_amu_topology_.cores[idx]; in fconf_populate_amu_cpu()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/arm_fpga/ |
| A D | index.rst.txt | 5 testing and bringup of new cores. With that focus, peripheral support is
22 As the number and topology layout of the CPU cores differs significantly
32 internal list, but for new or experimental cores this creates a lot of
|
| /trusted-firmware-a/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 5 testing and bringup of new cores. With that focus, peripheral support is
22 As the number and topology layout of the CPU cores differs significantly
32 internal list, but for new or experimental cores this creates a lot of
|