| /trusted-firmware-a/fdts/ |
| A D | cot_descriptors.dtsi | 18 antirollback-counter = <&trusted_nv_counter>;
37 antirollback-counter = <&trusted_nv_counter>;
51 antirollback-counter = <&trusted_nv_counter>;
62 antirollback-counter = <&trusted_nv_counter>;
73 antirollback-counter = <&trusted_nv_counter>;
83 antirollback-counter = <&trusted_nv_counter>;
97 antirollback-counter = <&trusted_nv_counter>;
108 antirollback-counter = <&trusted_nv_counter>;
128 antirollback-counter = <&non_trusted_nv_counter>;
154 antirollback-counter = <&trusted_nv_counter>;
[all …]
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| A D | tc.dts | 87 mpmm_gear0: counter@0 {
93 mpmm_gear1: counter@1 {
99 mpmm_gear2: counter@2 {
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/fconf/ |
| A D | amu-bindings.rst.txt | 37 An ``amu`` node describes the layout and meaning of the auxiliary counter
53 ``/cpus/amus/amu*/counter*`` node properties
56 A ``counter`` node describes an auxiliary counter belonging to the parent |AMU|
62 | ``reg`` | R | array | Represents the counter register |
66 | | | | indicates that this counter should |
87 counterX: counter@0 {
93 counterY: counter@1 {
104 counterZ: counter@0 {
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| /trusted-firmware-a/docs/components/fconf/ |
| A D | amu-bindings.rst | 37 An ``amu`` node describes the layout and meaning of the auxiliary counter
53 ``/cpus/amus/amu*/counter*`` node properties
56 A ``counter`` node describes an auxiliary counter belonging to the parent |AMU|
62 | ``reg`` | R | array | Represents the counter register |
66 | | | | indicates that this counter should |
87 counterX: counter@0 {
93 counterY: counter@1 {
104 counterZ: counter@0 {
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| /trusted-firmware-a/drivers/mentor/i2c/ |
| A D | mi2cv.c | 490 uint32_t counter = 0; in i2c_read() local
499 counter); in i2c_read()
505 if (counter > 0) in i2c_read()
507 counter++; in i2c_read()
538 } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); in i2c_read()
540 if (counter == I2C_MAX_RETRY_CNT) { in i2c_read()
569 uint32_t counter = 0; in i2c_write() local
578 if (counter > 0) in i2c_write()
580 counter++; in i2c_write()
604 } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); in i2c_write()
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | cot-binding.rst.txt | 81 - antirollback-counter
86 counter and it is an optional property.
89 counter sub-node present in 'non-volatile counters' node.
139 antirollback-counter = <&trusted_nv_counter>;
153 antirollback-counter = <&trusted_nv_counter>;
245 non-volatile counter node binding definition
258 Definition: must be "arm, non-volatile-counter"
268 of non-volatile counter register
283 Usage: Required for every nv-counter with unique id.
309 compatible = "arm, non-volatile-counter";
[all …]
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| /trusted-firmware-a/docs/components/ |
| A D | cot-binding.rst | 81 - antirollback-counter
86 counter and it is an optional property.
89 counter sub-node present in 'non-volatile counters' node.
139 antirollback-counter = <&trusted_nv_counter>;
153 antirollback-counter = <&trusted_nv_counter>;
245 non-volatile counter node binding definition
258 Definition: must be "arm, non-volatile-counter"
268 of non-volatile counter register
283 Usage: Required for every nv-counter with unique id.
309 compatible = "arm, non-volatile-counter";
[all …]
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| /trusted-firmware-a/docs/perf/ |
| A D | performance-monitoring-unit.rst | 7 This document gives an overview of the PMU counter configuration to assist with
22 - A dedicated cycle counter: ``PMCCNTR``.
46 Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
47 configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
119 - Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
121 In other words, the counter will not increment at any privilege level or
127 - If set to ``1`` enables the cycle counter ``PMCCNTR``.
134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/perf/ |
| A D | performance-monitoring-unit.rst.txt | 7 This document gives an overview of the PMU counter configuration to assist with
22 - A dedicated cycle counter: ``PMCCNTR``.
46 Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
47 configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
119 - Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
121 In other words, the counter will not increment at any privilege level or
127 - If set to ``1`` enables the cycle counter ``PMCCNTR``.
134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
|
| /trusted-firmware-a/tools/cert_create/src/ |
| A D | ext.c | 243 ASN1_INTEGER *counter; in ext_new_nvcounter() local
248 counter = ASN1_INTEGER_new(); in ext_new_nvcounter()
249 ASN1_INTEGER_set(counter, value); in ext_new_nvcounter()
250 sz = i2d_ASN1_INTEGER(counter, &p); in ext_new_nvcounter()
257 ASN1_INTEGER_free(counter); in ext_new_nvcounter()
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| /trusted-firmware-a/lib/extensions/amu/ |
| A D | amu.mk | 14 …$(error AMU auxiliary counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`) requires AMU support (`ENA…
20 …r AMU FCONF support (`ENABLE_AMU_FCONF`) is not necessary when auxiliary counter support (`ENABLE_…
|
| /trusted-firmware-a/lib/mpmm/ |
| A D | mpmm.mk | 16 …$(error MPMM support (`ENABLE_MPM`) requires auxiliary AMU counter support (`ENABLE_AMU_AUXILIARY_…
|
| /trusted-firmware-a/docs/process/ |
| A D | security-hardening.rst | 85 - ``SCCD`` for the cycle counter.
92 - Prohibit general event counters and the cycle counter:
109 - Prohibit cycle counter: ``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1``.
115 - Prohibit cycle counter: ``MDCR_EL3.SCCD == 1``
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/process/ |
| A D | security-hardening.rst.txt | 85 - ``SCCD`` for the cycle counter.
92 - Prohibit general event counters and the cycle counter:
109 - Prohibit cycle counter: ``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1``.
115 - Prohibit cycle counter: ``MDCR_EL3.SCCD == 1``
|
| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-5.rst | 32 bit is set to zero, the cycle counter (when enabled) counts during secure world
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-5.rst.txt | 32 bit is set to zero, the cycle counter (when enabled) counts during secure world
|
| /trusted-firmware-a/drivers/st/clk/ |
| A D | stm32mp1_clk.c | 1678 unsigned long long counter; in stm32mp1_stgen_config() local
1688 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); in stm32mp1_stgen_config()
1689 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; in stm32mp1_stgen_config()
1690 counter = (counter * rate / cntfid0); in stm32mp1_stgen_config()
1692 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); in stm32mp1_stgen_config()
1693 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); in stm32mp1_stgen_config()
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| /trusted-firmware-a/docs/build/latex/ |
| A D | sphinxmanual.cls | 96 % before resetting page counter, let's do the right thing.
|
| A D | sphinxlatexnumfig.sty | 15 % code listings (literalblock counter). User or extension re-definitions of
|
| A D | sphinxlatexgraphics.sty | 113 % tabulary expands twice contents, we need to prevent double counter stepping
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | glossary.rst.txt | 20 that exposes CPU core runtime metrics as a set of counter registers.
|
| /trusted-firmware-a/docs/ |
| A D | glossary.rst | 20 that exposes CPU core runtime metrics as a set of counter registers.
|
| /trusted-firmware-a/docs/getting_started/ |
| A D | porting-guide.rst | 744 non-volatile counter value stored in the platform in the second argument. The
745 cookie in the first argument may be used to select the counter in case the
762 counter value in the platform. The cookie in the first argument may be used to
763 select the counter (as explained in plat_get_nv_ctr()). The second argument is
764 the updated counter value to be written to the NV counter.
782 descriptor and may be used to decide if the counter is allowed to be
783 updated or not. The third argument is the updated counter value to
784 be written to the NV counter.
786 The function returns 0 on success. Any other value means the counter value
1945 - Grant access to the system counter timer module
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | porting-guide.rst.txt | 744 non-volatile counter value stored in the platform in the second argument. The
745 cookie in the first argument may be used to select the counter in case the
762 counter value in the platform. The cookie in the first argument may be used to
763 select the counter (as explained in plat_get_nv_ctr()). The second argument is
764 the updated counter value to be written to the NV counter.
782 descriptor and may be used to decide if the counter is allowed to be
783 updated or not. The third argument is the updated counter value to
784 be written to the NV counter.
786 The function returns 0 on success. Any other value means the counter value
1945 - Grant access to the system counter timer module
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/threat_model/ |
| A D | threat_model.rst.txt | 317 | | compared with the corresponding NV counter stored|
318 | | in hardware to make sure the new counter value is|
319 | | larger or equal to the current counter value. |
|