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Searched refs:cpu (Results 1 – 25 of 136) sorted by relevance

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/trusted-firmware-a/plat/mediatek/mt8192/
A Dplat_pm.c76 gicv3_cpuif_disable(cpu); in plat_cpu_pwrdwn_common()
77 gicv3_rdistif_off(cpu); in plat_cpu_pwrdwn_common()
79 ptp3_deinit(cpu); in plat_cpu_pwrdwn_common()
98 gicv3_rdistif_on(cpu); in plat_cpu_pwron_common()
105 ptp3_init(cpu); in plat_cpu_pwron_common()
260 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend()
264 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend()
269 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend()
281 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend_finish()
286 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend_finish()
[all …]
/trusted-firmware-a/plat/mediatek/mt8195/
A Dplat_pm.c76 gicv3_cpuif_disable(cpu); in plat_cpu_pwrdwn_common()
77 gicv3_rdistif_off(cpu); in plat_cpu_pwrdwn_common()
90 ptp3_core_init(cpu); in plat_cpu_pwron_common()
99 gicv3_rdistif_on(cpu); in plat_cpu_pwron_common()
100 gicv3_cpuif_enable(cpu); in plat_cpu_pwron_common()
258 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend()
262 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend()
267 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend()
279 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend_finish()
284 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); in plat_power_domain_suspend_finish()
[all …]
/trusted-firmware-a/plat/hisilicon/hikey/
A Dhisi_ipc.c48 if (cpu == i) in hisi_cpus_pd_in_cluster_besides_curr()
64 return (val == (0x8 << (cpu * 4))); in hisi_cpus_powered_off_besides_curr()
104 offset = cluster * 16 + cpu * 4; in hisi_ipc_cpu_on_off()
106 offset = cluster * 16 + cpu * 4 + 1; in hisi_ipc_cpu_on_off()
116 hisi_ipc_send(cpu_ipc_num[cluster][cpu]); in hisi_ipc_cpu_on_off()
121 hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_ON); in hisi_ipc_cpu_on()
126 hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_OFF); in hisi_ipc_cpu_off()
148 hisi_ipc_send(cpu_ipc_num[cluster][cpu]); in hisi_ipc_cluster_on_off()
166 offset = cluster * 16 + cpu * 4 + 2; in hisi_ipc_cpu_suspend()
174 hisi_ipc_send(cpu_ipc_num[cluster][cpu]); in hisi_ipc_cpu_suspend()
[all …]
A Dhikey_pm.c34 int cpu, cluster; in hikey_pwr_domain_on() local
38 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on()
41 hisi_ipc_cluster_on(cpu, cluster); in hikey_pwr_domain_on()
45 hisi_ipc_cpu_on(cpu, cluster); in hikey_pwr_domain_on()
53 int cpu, cluster; in hikey_pwr_domain_on_finish() local
57 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on_finish()
79 int cpu, cluster; in hikey_pwr_domain_off() local
83 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_off()
86 hisi_ipc_cpu_off(cpu, cluster); in hikey_pwr_domain_off()
136 unsigned int cluster, cpu; in hikey_pwr_domain_suspend_finish() local
[all …]
/trusted-firmware-a/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
32 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
80 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate()
117 void spm_poweron_cpu(unsigned int cluster, unsigned int cpu) in spm_poweron_cpu() argument
119 uintptr_t cpu_pwr_con = per_cpu(cluster, cpu, SPM_CPU_PWR); in spm_poweron_cpu()
122 if (cpu >= 4U) { in spm_poweron_cpu()
128 while (!spm_get_cpu_powerstate(cluster, cpu)) { in spm_poweron_cpu()
140 void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu) in spm_poweroff_cpu() argument
[all …]
A Dmtspmc.h14 void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
15 void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
20 bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
24 void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
25 void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
26 uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
28 void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
29 void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
/trusted-firmware-a/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc.c40 void spm_enable_cpu_auto_off(int cluster, int cpu) in spm_enable_cpu_auto_off() argument
56 void spm_set_cpu_power_off(int cluster, int cpu) in spm_set_cpu_power_off() argument
81 assert(cpu >= 0 && cpu < 4); in mcucfg_set_bootaddr()
82 reg = mp2_bootreg[cpu]; in mcucfg_set_bootaddr()
84 reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); in mcucfg_set_bootaddr()
98 assert(cpu >= 0 && cpu < 4); in mcucfg_get_bootaddr()
99 reg = mp2_bootreg[cpu]; in mcucfg_get_bootaddr()
101 reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); in mcucfg_get_bootaddr()
151 i = 1 << (i + cpu); in spm_get_cpu_powerstate()
203 void spm_poweron_cpu(int cluster, int cpu) in spm_poweron_cpu() argument
[all …]
A Dmtspmc.h23 void spm_poweron_cpu(int cluster, int cpu);
24 void spm_poweroff_cpu(int cluster, int cpu);
29 int spm_get_cpu_powerstate(int cluster, int cpu);
33 void spm_enable_cpu_auto_off(int cluster, int cpu);
34 void spm_disable_cpu_auto_off(int cluster, int cpu);
35 void spm_set_cpu_power_off(int cluster, int cpu);
38 void mcucfg_init_archstate(int cluster, int cpu, int arm64);
39 void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
40 uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
/trusted-firmware-a/plat/mediatek/mt8195/drivers/spm/constraints/
A Dmt_spm_rc_internal.h20 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
21 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
24 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
27 int spm_run_rc_dram(unsigned int cpu, int state_id);
28 int spm_reset_rc_dram(unsigned int cpu, int state_id);
31 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
34 int spm_run_rc_syspll(unsigned int cpu, int state_id);
35 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
38 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
41 int spm_run_rc_bus26m(unsigned int cpu, int state_id);
[all …]
A Dmt_spm_rc_cpu_buck_ldo.c53 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id) in spm_is_valid_rc_cpu_buck_ldo() argument
55 (void)cpu; in spm_is_valid_rc_cpu_buck_ldo()
68 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id) in spm_run_rc_cpu_buck_ldo() argument
70 (void)cpu; in spm_run_rc_cpu_buck_ldo()
92 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id) in spm_reset_rc_cpu_buck_ldo() argument
94 (void)cpu; in spm_reset_rc_cpu_buck_ldo()
/trusted-firmware-a/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc.c18 void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu) in mcucfg_disable_gic_wakeup() argument
23 void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu) in mcucfg_enable_gic_wakeup() argument
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
80 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate()
124 void spm_poweron_cpu(uint32_t cluster, uint32_t cpu) in spm_poweron_cpu() argument
127 if (cpu >= 4U) { in spm_poweron_cpu()
134 while (!spm_get_cpu_powerstate(cluster, cpu)) { in spm_poweron_cpu()
140 if (cpu >= 4U) { in spm_poweron_cpu()
141 mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3)); in spm_poweron_cpu()
[all …]
A Dmtspmc.h14 void spm_poweron_cpu(uint32_t cluster, uint32_t cpu);
15 void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu);
20 bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu);
24 void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64);
25 void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr);
26 uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu);
28 void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu);
29 void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu);
/trusted-firmware-a/plat/mediatek/mt8192/drivers/spm/constraints/
A Dmt_spm_rc_internal.h22 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
23 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
26 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
29 int spm_run_rc_dram(unsigned int cpu, int state_id);
30 int spm_reset_rc_dram(unsigned int cpu, int state_id);
33 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
36 int spm_run_rc_syspll(unsigned int cpu, int state_id);
37 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
40 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
43 int spm_run_rc_bus26m(unsigned int cpu, int state_id);
[all …]
/trusted-firmware-a/plat/nvidia/tegra/drivers/flowctrl/
A Dflowctrl.c99 if (i == cpu) in tegra_fc_ccplex_pgexit_lock()
125 int cpu = mpidr & MPIDR_CPU_MASK; in tegra_fc_cpu_powerdn() local
128 tegra_fc_prepare_suspend(cpu, 0); in tegra_fc_cpu_powerdn()
141 tegra_fc_cc4_ctrl(cpu, 0); in tegra_fc_cluster_idle()
162 tegra_fc_cc4_ctrl(cpu, 0); in tegra_fc_cluster_powerdn()
185 if (i == cpu) in tegra_fc_is_ccx_allowed()
208 tegra_fc_cc4_ctrl(cpu, 0); in tegra_fc_soc_powerdn()
222 void tegra_fc_cpu_on(int cpu) in tegra_fc_cpu_on() argument
231 void tegra_fc_cpu_off(int cpu) in tegra_fc_cpu_off() argument
241 tegra_fc_cpu_csr(cpu, val); in tegra_fc_cpu_off()
[all …]
/trusted-firmware-a/plat/mediatek/mt8183/
A Dplat_pm.c112 #define CPU_IDX(cluster, cpu) ((cluster << 2) + cpu) argument
140 int my_idx = (cluster << 2) + cpu; in clst_single_pwr()
149 int my_idx = (cluster << 2) + cpu; in clst_single_on()
224 CPU_IDX(cluster, cpu), OFF); in mcdi_ctrl_before_hotplug_off()
271 spm_poweron_cpu(cluster, cpu); in hotplug_ctrl_cpu_on()
292 CPU_IDX(cluster, cpu), OFF); in hotplug_ctrl_cluster_cpu_off()
305 int cpu = MPIDR_AFFLVL0_VAL(mpidr); in plat_mtk_power_domain_on() local
321 hotplug_ctrl_cpu_on(cluster, cpu); in plat_mtk_power_domain_on()
329 int cpu = MPIDR_AFFLVL0_VAL(mpidr); in plat_mtk_power_domain_off() local
334 clst_single_on(cluster, cpu)); in plat_mtk_power_domain_off()
[all …]
/trusted-firmware-a/plat/arm/board/tc/fdts/
A Dtc_spmc_manifest.dts59 CPU0:cpu@0 {
60 device_type = "cpu";
70 CPU7:cpu@700 {
71 device_type = "cpu";
77 CPU6:cpu@600 {
78 device_type = "cpu";
84 CPU5:cpu@500 {
91 CPU4:cpu@400 {
98 CPU3:cpu@300 {
105 CPU2:cpu@200 {
[all …]
A Dtc_spmc_optee_sp_manifest.dts58 CPU0:cpu@0 {
59 device_type = "cpu";
69 CPU7:cpu@700 {
70 device_type = "cpu";
76 CPU6:cpu@600 {
77 device_type = "cpu";
83 CPU5:cpu@500 {
90 CPU4:cpu@400 {
97 CPU3:cpu@300 {
104 CPU2:cpu@200 {
[all …]
/trusted-firmware-a/plat/mediatek/mt8192/drivers/mcdi/
A Dmt_cpu_pm.c25 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
30 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
32 mtk_cpc_core_on_hint_clr(cpu); in pwr_state_reflect()
41 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
46 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
54 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
59 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
64 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
75 static int pwr_mcusys_pwron_finished(unsigned int cpu, in pwr_mcusys_pwron_finished() argument
84 mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id); in pwr_mcusys_pwron_finished()
[all …]
/trusted-firmware-a/plat/mediatek/mt8195/drivers/mcdi/
A Dmt_cpu_pm.c25 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
30 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
32 mtk_cpc_core_on_hint_clr(cpu); in pwr_state_reflect()
41 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
46 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
54 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
59 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
64 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
75 static int pwr_mcusys_pwron_finished(unsigned int cpu, in pwr_mcusys_pwron_finished() argument
84 mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id); in pwr_mcusys_pwron_finished()
[all …]
/trusted-firmware-a/plat/mediatek/mt8192/include/
A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
34 int (*pwr_cluster_on)(unsigned int cpu,
36 int (*pwr_cluster_dwn)(unsigned int cpu,
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
40 int (*pwr_mcusys_on_finished)(unsigned int cpu,
42 int (*pwr_mcusys_dwn)(unsigned int cpu,
/trusted-firmware-a/plat/mediatek/mt8195/include/
A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
34 int (*pwr_cluster_on)(unsigned int cpu,
36 int (*pwr_cluster_dwn)(unsigned int cpu,
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
40 int (*pwr_mcusys_on_finished)(unsigned int cpu,
42 int (*pwr_mcusys_dwn)(unsigned int cpu,
/trusted-firmware-a/plat/rockchip/rk3368/drivers/pmu/
A Dpmu.c241 uint32_t cpu, in cpus_id_power_domain() argument
249 pd = PD_CPUB0 + cpu; in cpus_id_power_domain()
251 pd = PD_CPUL0 + cpu; in cpus_id_power_domain()
267 uint32_t boot_cpu, boot_cluster, cpu; in nonboot_cpus_off() local
273 for (cpu = 0; cpu < PLATFORM_CLUSTER0_CORE_COUNT; cpu++) { in nonboot_cpus_off()
279 for (cpu = 0; cpu < PLATFORM_CLUSTER1_CORE_COUNT; cpu++) { in nonboot_cpus_off()
298 uint32_t cpu, cluster; in rockchip_soc_cores_pwr_dm_on() local
301 cpu = MPIDR_AFFLVL0_VAL(mpidr); in rockchip_soc_cores_pwr_dm_on()
362 uint32_t cpu; in plat_rockchip_pmu_init() local
367 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) in plat_rockchip_pmu_init()
[all …]
/trusted-firmware-a/fdts/
A Dtc.dts28 cpu-map {
31 cpu = <&CPU0>;
34 cpu = <&CPU1>;
37 cpu = <&CPU2>;
40 cpu = <&CPU3>;
43 cpu = <&CPU4>;
107 CPU0:cpu@0 {
119 CPU1:cpu@100 {
131 CPU2:cpu@200 {
143 CPU3:cpu@300 {
[all …]
/trusted-firmware-a/plat/hisilicon/hikey/include/
A Dhisi_ipc.h37 void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster);
38 void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster);
39 void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster);
40 void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster);
41 void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster);
42 void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster);
/trusted-firmware-a/plat/allwinner/common/
A Dsunxi_pm.c34 for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) { in plat_setup_psci_ops() local
35 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu), in plat_setup_psci_ops()
37 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu), in plat_setup_psci_ops()

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