/trusted-firmware-a/plat/marvell/armada/common/ |
A D | marvell_ddr_info.c | 15 #define DRAM_CH0_MMAP_LOW_REG(iface, cs, base) \ argument 17 #define DRAM_CH0_MMAP_HIGH_REG(iface, cs, base) \ argument 18 (DRAM_CH0_MMAP_LOW_REG(iface, cs, base) + 4) 29 #define DRAM_CS_ENABLED(iface, cs, base) \ argument 30 (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \ 32 #define GET_DRAM_REGION_SIZE_CODE(iface, cs, base) \ argument 81 uint8_t cs, iface; in mvebu_get_dram_size() local 84 for (cs = 0; cs < DRAM_MAX_CS_NUM; cs++) { in mvebu_get_dram_size() 87 if (!DRAM_CS_ENABLED(iface, cs, ap_base_addr)) in mvebu_get_dram_size() 94 GET_DRAM_REGION_SIZE_CODE(iface, cs, in mvebu_get_dram_size() [all …]
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/trusted-firmware-a/plat/nxp/soc-lx2160a/lx2160aqds/ |
A D | ddr_init.c | 27 .cs[0].bnds = U(0x03FF), 28 .cs[1].bnds = U(0x03FF), 31 .cs[2].bnds = U(0x00), 32 .cs[3].bnds = U(0x00), 33 .cs[2].config = U(0x00), 34 .cs[3].config = U(0x00), 78 .cs[0].bnds = U(0x03FF), 82 .cs[2].bnds = U(0x00), 83 .cs[3].bnds = U(0x00), 133 .cs[2].bnds = U(0x00), [all …]
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/trusted-firmware-a/plat/nxp/soc-lx2160a/lx2162aqds/ |
A D | ddr_init.c | 27 .cs[0].bnds = U(0x03FFU), 28 .cs[1].bnds = U(0x03FF), 31 .cs[2].bnds = U(0x00), 32 .cs[3].bnds = U(0x00), 33 .cs[2].config = U(0x00), 34 .cs[3].config = U(0x00), 78 .cs[0].bnds = U(0x03FF), 82 .cs[2].bnds = U(0x00), 83 .cs[3].bnds = U(0x00), 133 .cs[2].bnds = U(0x00), [all …]
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/trusted-firmware-a/drivers/renesas/common/ddr/ddr_b/ |
A D | boot_init_dram.c | 2340 uint32_t ch, cs; in dbsc_regset_post() local 2347 for (cs = 0; cs < CS_CNT; cs++) { in dbsc_regset_post() 2352 cs); in dbsc_regset_post() 2390 for (cs = 0; cs < CS_CNT; cs++) { in dbsc_regset_post() 3418 for (cs = 0; cs < CS_CNT; cs++) { in wdqdm_man1() 4107 for (cs = 0; cs < CS_CNT; cs++) { in adjust_wpath_latency() 4110 cs); in adjust_wpath_latency() 4133 uint32_t ch, cs; in rcar_dram_init() local 4224 for (cs = 0; cs < CS_CNT; cs++) { in rcar_dram_init() 4229 for (cs = 0; cs < CS_CNT; cs++) in rcar_dram_init() [all …]
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A D | boot_init_dram_regdef.h | 31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
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/trusted-firmware-a/drivers/nxp/ddr/nxp-ddr/ |
A D | ddrc.c | 221 (regs->cs[i].bnds & U(0xfffefffe)) >> 1U); in ddrc_set_regs() 223 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds); in ddrc_set_regs() 405 (regs->cs[i].config & ~CTLR_INTLV_MASK)); in ddrc_set_regs() 407 ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config); in ddrc_set_regs() 456 if ((regs->cs[i].config & 0x80000000) == 0) { in ddrc_set_regs() 460 ((regs->cs[i].config >> 14) & 0x3) + 2 + in ddrc_set_regs() 461 ((regs->cs[i].config >> 8) & 0x7) + 12 + in ddrc_set_regs() 462 ((regs->cs[i].config >> 4) & 0x3) + 0 + in ddrc_set_regs() 463 ((regs->cs[i].config >> 0) & 0x7) + 8 + in ddrc_set_regs() 503 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds); in ddrc_set_regs() [all …]
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A D | regs.c | 59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config() 70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config() 903 regs->cs[i].bnds = ((sa & 0xffff) << 16) | in cal_ddr_csn_bnds() 908 regs->cs[i].bnds = 0xffffffff; in cal_ddr_csn_bnds() 920 const unsigned int cs0_config = regs->cs[0].config; in cal_ddr_addr_dec() 925 unsigned int cs; in cal_ddr_addr_dec() local 953 cs = 1; in cal_ddr_addr_dec() 956 cs = 2; in cal_ddr_addr_dec() 959 cs = 0; in cal_ddr_addr_dec() 1003 if (cs != 0U) { in cal_ddr_addr_dec() [all …]
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/trusted-firmware-a/lib/debugfs/ |
A D | devfip.c | 191 chan_t cs; in fipread() local 208 if (clone(fip->c, &cs) == NULL) { in fipread() 226 if (devtab[cs.index]->seek(&cs, off, KSEEK_SET) < 0) { in fipread() 230 n = devtab[cs.index]->read(&cs, buf, n); in fipread()
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/trusted-firmware-a/plat/nxp/soc-lx2160a/lx2160ardb/ |
A D | ddr_init.c | 26 .cs[0].config = U(0xA8050322), 27 .cs[1].config = U(0x80000322), 28 .cs[0].bnds = U(0x3FF), 29 .cs[1].bnds = U(0x3FF),
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/trusted-firmware-a/drivers/mtd/spi-mem/ |
A D | spi_mem.c | 28 unsigned int cs; member 165 ret = ops->claim_bus(spi_slave.cs); in spi_mem_exec_op() 218 spi_slave.cs = fdt32_to_cpu(*cuint); in spi_mem_init_slave()
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/trusted-firmware-a/drivers/st/fmc/ |
A D | stm32_fmc2_nand.c | 149 struct stm32_fmc2_cs_reg cs[MAX_CS]; member 570 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; in stm32_fmc2_read_data() 617 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; in stm32_fmc2_write_data() 707 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, in stm32_fmc2_exec() 712 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, in stm32_fmc2_exec() 865 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) + in stm32_fmc2_init() 872 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) + in stm32_fmc2_init() 879 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) + in stm32_fmc2_init()
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/trusted-firmware-a/plat/nxp/soc-ls1028a/ls1028ardb/ |
A D | ddr_init.c | 16 .cs[0].config = U(0x80040422), 17 .cs[0].bnds = U(0xFF),
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/trusted-firmware-a/drivers/renesas/common/ |
A D | ddr_regs.h | 16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
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/trusted-firmware-a/include/drivers/ |
A D | spi_mem.h | 94 int (*claim_bus)(unsigned int cs);
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/trusted-firmware-a/drivers/brcm/spi/ |
A D | iproc_qspi.h | 100 int iproc_qspi_setup(uint32_t bus, uint32_t cs,
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A D | iproc_qspi.c | 29 int iproc_qspi_setup(uint32_t bus, uint32_t cs, uint32_t max_hz, uint32_t mode) in iproc_qspi_setup() argument
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/trusted-firmware-a/drivers/st/spi/ |
A D | stm32_qspi.c | 341 static int stm32_qspi_claim_bus(unsigned int cs) in stm32_qspi_claim_bus() argument 345 if (cs >= QSPI_MAX_CHIP) { in stm32_qspi_claim_bus() 351 if (cs == 1U) { in stm32_qspi_claim_bus()
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/trusted-firmware-a/plat/intel/soc/common/drivers/qspi/ |
A D | cadence_qspi.c | 99 int cad_qspi_stig_cmd_helper(int cs, uint32_t cmd) in cad_qspi_stig_cmd_helper() argument 106 & CAD_QSPI_CFG_CS_MSK) | CAD_QSPI_CFG_CS(cs)); in cad_qspi_stig_cmd_helper() 500 void cad_qspi_set_chip_select(int cs) in cad_qspi_set_chip_select() argument 502 cad_qspi_cs = cs; in cad_qspi_set_chip_select()
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A D | cadence_qspi.h | 171 void cad_qspi_set_chip_select(int cs);
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/trusted-firmware-a/include/drivers/nxp/ddr/ |
A D | ddr.h | 54 } cs[MAX_CS_NUM]; member
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/trusted-firmware-a/plat/rockchip/rk3399/drivers/dram/ |
A D | dram_spec_timing.c | 130 uint32_t cs, ch; in get_max_die_capability() local 133 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { in get_max_die_capability() 136 dram_info[ch].per_die_capability[cs]); in get_max_die_capability()
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/trusted-firmware-a/docs/build/TF-A_2.5/_static/ |
A D | pygments.css | 17 .highlight .cs { color: #408090; background-color: #fff0f0 } /* Comment.Special */
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/trusted-firmware-a/docs/build/latex/ |
A D | sphinxhighlight.sty | 20 \@namedef{PYG@tok@cs}{\def\PYG@tc##1{\textcolor[rgb]{0.25,0.50,0.56}{##1}}\def\PYG@bc##1{{\setlengt…
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/trusted-firmware-a/build/qemu/release/bl2/ |
A D | bl2.dump | 2341 e01cb88: 1a812000 csel w0, w0, w1, cs // cs = hs, nlast 3152 e01d6dc: 54000082 b.cs e01d6ec <zero_normalmem+0x70> // b.hs, b.nlast 3158 e01d6f4: 540000a2 b.cs e01d708 <zero_normalmem+0x8c> // b.hs, b.nlast 3165 e01d710: 54000082 b.cs e01d720 <zero_normalmem+0xa4> // b.hs, b.nlast 3181 e01d750: 54fffe82 b.cs e01d720 <zero_normalmem+0xa4> // b.hs, b.nlast 3371 e01d9c0: 1a9f37e1 cset w1, cs // cs = hs, nlast 3375 e01d9d0: 540000a2 b.cs e01d9e4 <fdt_offset_ptr+0x48> // b.hs, b.nlast 3387 e01da00: 54ffff22 b.cs e01d9e4 <fdt_offset_ptr+0x48> // b.hs, b.nlast 3689 e01de60: 54000162 b.cs e01de8c <fdt_mem_rsv+0x50> // b.hs, b.nlast 3697 e01de80: 9a9f2000 csel x0, x0, xzr, cs // cs = hs, nlast [all …]
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/trusted-firmware-a/build/qemu/release/bl31/ |
A D | bl31.dump | 1470 e040934: 54ffffa2 b.cs e040928 <loop3_isw> // b.hs, b.nlast 1472 e04093c: 54ffff42 b.cs e040924 <dcsw_loop_table> // b.hs, b.nlast 1482 e040954: 54ffffa2 b.cs e040948 <loop3_cisw> // b.hs, b.nlast 1484 e04095c: 54ffff42 b.cs e040944 <loop2_cisw> // b.hs, b.nlast 1494 e040974: 54ffffa2 b.cs e040968 <loop3_csw> // b.hs, b.nlast 1496 e04097c: 54ffff42 b.cs e040964 <loop2_csw> // b.hs, b.nlast 2147 e0411e0: 54000082 b.cs e0411f0 <zero_normalmem+0x70> // b.hs, b.nlast 2153 e0411f8: 540000a2 b.cs e04120c <zero_normalmem+0x8c> // b.hs, b.nlast 2160 e041214: 54000082 b.cs e041224 <zero_normalmem+0xa4> // b.hs, b.nlast 2198 e0412a4: 1a832021 csel w1, w1, w3, cs // cs = hs, nlast [all …]
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