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Searched refs:ctrl (Results 1 – 13 of 13) sorted by relevance

/trusted-firmware-a/drivers/brcm/emmc/
A Demmc_chal_sd.c175 handle->ctrl.sdRegBaseAddr = sdBase; in chal_sd_setup_handler()
176 handle->ctrl.hostRegBaseAddr = hostBase; in chal_sd_setup_handler()
177 handle->ctrl.present = 0; in chal_sd_setup_handler()
178 handle->ctrl.rca = 0; in chal_sd_setup_handler()
179 handle->ctrl.blkGapEnable = 0; in chal_sd_setup_handler()
180 handle->ctrl.cmdStatus = 0; in chal_sd_setup_handler()
380 handle->ctrl.eventList = 0; in chal_sd_start()
538 handle->ctrl.blkReg); in chal_sd_send_cmd()
543 handle->ctrl.argReg = argument; in chal_sd_send_cmd()
556 handle->ctrl.cmdIndex = cmd_idx; in chal_sd_send_cmd()
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A Demmc_csl_sdcard.c196 handle->device->ctrl.argReg = 0; in abort_err()
205 handle->device->ctrl.cmdIndex, in abort_err()
425 handle->device->ctrl.ocr = ocr; in init_mmc_card()
505 handle->device->ctrl.rca = 0; in reset_card()
671 if (handle->device->ctrl.cmdStatus) { in write_buffer()
734 if (handle->device->ctrl.cmdStatus) { in read_buffer()
763 if (handle->device->ctrl.cmdStatus) { in read_buffer()
952 (handle->device->ctrl.sdRegBaseAddr + in pstate_log()
955 (handle->device->ctrl.sdRegBaseAddr + in pstate_log()
1004 handle->device->ctrl.cmdStatus = in wait_for_event()
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A Demmc_csl_sdcmd.c76 handle->device->ctrl.rca = 0x5; in sd_cmd3()
87 handle->device->ctrl.rca = 0; in sd_cmd3()
433 handle->device->ctrl.rca, res); in card_sts_resp()
738 handle->device->ctrl.argReg = argument; in send_cmd()
740 handle->device->ctrl.argReg, options); in send_cmd()
742 handle->device->ctrl.cmdIndex = cmdIndex; in send_cmd()
779 handle->device->ctrl.cmdIndex, in send_cmd()
808 } else if (handle->device->ctrl.cmdStatus && in send_cmd()
817 if ((handle->device->ctrl.cmdIndex == 1) || in send_cmd()
837 handle->device->ctrl.blkReg = 0; in send_cmd()
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A Demmc_pboot_hal_memory_drv.c338 if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) { in sdio_read()
344 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) { in sdio_read()
387 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) in sdio_read()
412 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) in sdio_read()
465 if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) { in sdio_write()
471 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) { in sdio_write()
532 if (p_sdhandle->device->ctrl.ocr & in sdio_write()
556 if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) in sdio_write()
/trusted-firmware-a/drivers/marvell/
A Damb_adec.c77 uint32_t ctrl, base, size; in amb_enable_win() local
85 ctrl = (size << AMB_SIZE_OFFSET) | (win->target_id << AMB_ATTR_OFFSET); in amb_enable_win()
89 mmio_write_32(AMB_WIN_CR_OFFSET(win_num), ctrl); in amb_enable_win()
92 ctrl |= WIN_ENABLE_BIT; in amb_enable_win()
93 mmio_write_32(AMB_WIN_CR_OFFSET(win_num), ctrl); in amb_enable_win()
99 uint32_t ctrl, base, win_id, attr; in dump_amb_adec() local
106 ctrl = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in dump_amb_adec()
107 if (ctrl & WIN_ENABLE_BIT) { in dump_amb_adec()
109 attr = (ctrl >> AMB_ATTR_OFFSET) & AMB_ATTR_MASK; in dump_amb_adec()
110 size_count = (ctrl >> AMB_SIZE_OFFSET) & AMB_SIZE_MASK; in dump_amb_adec()
/trusted-firmware-a/plat/marvell/armada/a3k/common/
A Dio_addr_dec.c40 uint32_t ctrl = 0; in set_io_addr_dec_win() local
44 ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << in set_io_addr_dec_win()
47 ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF; in set_io_addr_dec_win()
49 ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF; in set_io_addr_dec_win()
64 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
66 ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF; in set_io_addr_dec_win()
68 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
/trusted-firmware-a/plat/brcm/board/stingray/src/
A Dpaxb.c383 mmio_clrbits_32(ctrl, PCIE_CORE_SOFT_RST); in pcie_core_soft_reset()
388 mmio_setbits_32(ctrl, PCIE_CORE_SOFT_RST); in pcie_core_soft_reset()
398 mmio_setbits_32(ctrl, mask); in pcie_core_pwron_switch()
411 static int pcie_core_pwr_seq(uintptr_t ctrl, uintptr_t status) in pcie_core_pwr_seq() argument
449 uintptr_t ctrl, status; in pcie_core_pwr_init() local
452 ctrl = (uintptr_t)(PCIE_CORE_MEM_PWR_BASE + offset); in pcie_core_pwr_init()
454 ret = pcie_core_pwr_seq(ctrl, status); in pcie_core_pwr_init()
461 ctrl = (uintptr_t)(PCIE_PAXB_MEM_PWR_BASE + offset); in pcie_core_pwr_init()
463 ret = pcie_core_pwr_seq(ctrl, status); in pcie_core_pwr_init()
470 ctrl = (uintptr_t)(PCIE_CORE_ISO_CFG_BASE + offset); in pcie_core_pwr_init()
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/trusted-firmware-a/drivers/rpi3/rng/
A Drpi3_rng.c19 uint32_t int_mask, ctrl; in rpi3_rng_initialize() local
22 ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); in rpi3_rng_initialize()
23 if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { in rpi3_rng_initialize()
/trusted-firmware-a/plat/imx/common/include/sci/svc/pad/
A Dsci_pad_api.h257 sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl);
277 sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
339 sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
366 uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
/trusted-firmware-a/plat/imx/common/sci/svc/pad/
A Dpad_rpc_clnt.c83 sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) in sc_pad_set_gp() argument
91 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_pad_set_gp()
101 sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl) in sc_pad_get_gp() argument
114 if (ctrl != NULL) { in sc_pad_get_gp()
115 *ctrl = RPC_U32(&msg, 0U); in sc_pad_get_gp()
162 sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, in sc_pad_set_all() argument
171 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_pad_set_all()
187 uint32_t *ctrl, sc_pad_wakeup_t *wakeup) in sc_pad_get_all() argument
200 if (ctrl != NULL) { in sc_pad_get_all()
201 *ctrl = RPC_U32(&msg, 0U); in sc_pad_get_all()
/trusted-firmware-a/plat/imx/common/include/sci/svc/misc/
A Dsci_misc_api.h121 sc_ctrl_t ctrl, uint32_t val);
141 sc_ctrl_t ctrl, uint32_t *val);
/trusted-firmware-a/plat/imx/common/sci/svc/misc/
A Dmisc_rpc_clnt.c32 sc_ctrl_t ctrl, uint32_t val) in sc_misc_set_control() argument
40 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_misc_set_control()
52 sc_ctrl_t ctrl, uint32_t *val) in sc_misc_get_control() argument
60 RPC_U32(&msg, 0U) = (uint32_t)ctrl; in sc_misc_get_control()
/trusted-firmware-a/include/drivers/brcm/emmc/
A Demmc_chal_sd.h166 struct sd_ctrl_info ctrl; /* SD info */ member

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