Searched refs:disable (Results 1 – 25 of 50) sorted by relevance
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| /trusted-firmware-a/fdts/ |
| A D | stm32mp15-pinctrl.dtsi | 24 bias-disable;
38 bias-disable;
47 bias-disable;
59 bias-disable;
77 bias-disable;
98 bias-disable;
104 bias-disable;
151 bias-disable;
157 bias-disable;
181 bias-disable;
[all …]
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| A D | stm32mp157c-lxa-mc1.dts | 54 disable-wp;
67 /delete-property/ bias-disable;
71 /delete-property/ bias-disable;
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| A D | stm32mp157c-odyssey.dts | 29 disable-wp;
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| A D | stm32mp15xx-dkx.dtsi | 302 disable-wp;
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| A D | stm32mp157c-ed1.dts | 312 disable-wp;
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| /trusted-firmware-a/plat/socionext/uniphier/ |
| A D | uniphier_cci.c | 38 void (*disable)(void); member
45 .disable = NULL,
50 .disable = __uniphier_cci_disable,
55 .disable = NULL,
79 if (uniphier_cci_ops.disable) in uniphier_cci_disable()
80 uniphier_cci_ops.disable(); in uniphier_cci_disable()
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| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-6.rst | 54 significantly more complex than the "MMU disable/enable" workaround. The latter
62 locally (for example by implementing "MMU disable/enable" itself), there is no
75 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
93 | ``PSCI_VERSION`` with "MMU disable/enable" | 930 |
95 | ``SMCCC_ARCH_WORKAROUND_1`` with "MMU disable/enable" | 386 |
104 performance and code size overhead. Platforms can choose to disable them at
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| A D | security-advisory-tfv-2.rst | 34 The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
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| A D | security-advisory-tfv-7.rst | 55 initialization, following every PE reset. No mechanism is provided to disable
78 lower exception levels to temporarily disable the mitigation in their execution
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-6.rst.txt | 54 significantly more complex than the "MMU disable/enable" workaround. The latter
62 locally (for example by implementing "MMU disable/enable" itself), there is no
75 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
93 | ``PSCI_VERSION`` with "MMU disable/enable" | 930 |
95 | ``SMCCC_ARCH_WORKAROUND_1`` with "MMU disable/enable" | 386 |
104 performance and code size overhead. Platforms can choose to disable them at
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| A D | security-advisory-tfv-2.rst.txt | 34 The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
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| A D | security-advisory-tfv-7.rst.txt | 55 initialization, following every PE reset. No mechanism is provided to disable
78 lower exception levels to temporarily disable the mitigation in their execution
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| /trusted-firmware-a/docs/plat/ |
| A D | meson-axg.rst | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| A D | meson-g12a.rst | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| A D | meson-gxbb.rst | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| A D | meson-gxl.rst | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | meson-axg.rst.txt | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| A D | meson-g12a.rst.txt | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| A D | meson-gxbb.rst.txt | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| A D | meson-gxl.rst.txt | 14 - Basic SIP services (read efuse data, enable/disable JTAG).
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| /trusted-firmware-a/services/std_svc/sdei/ |
| A D | sdei_intr_mgmt.c | 356 bool disable = false; in handle_masked_trigger() local
368 disable = true; in handle_masked_trigger()
373 if (disable) { in handle_masked_trigger()
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| /trusted-firmware-a/docs/build/latex/ |
| A D | sphinxlatexindbibtoc.sty | 39 % disable \@chappos in Appendix in pTeX
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | platform-interrupt-controller-API.rst.txt | 101 This API should disable the interrupt ID specified by the first parameter,
105 writes to GIC *Clear Enable Register* to disable the interrupt, and inserts
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| /trusted-firmware-a/docs/components/ |
| A D | platform-interrupt-controller-API.rst | 101 This API should disable the interrupt ID specified by the first parameter,
105 writes to GIC *Clear Enable Register* to disable the interrupt, and inserts
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| /trusted-firmware-a/docs/process/ |
| A D | security-hardening.rst | 103 - The only other way is to disable the ``PMCR_EL0.E`` bit upon entering
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