| /trusted-firmware-a/docs/resources/diagrams/plantuml/ |
| A D | fip-secure-partitions.puml | 163 signed_spkg_1 -down-> fiptool
164 signed_spkg_2 -down-> fiptool
165 fiptool -down-> fip
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/perf/ |
| A D | psci-performance-juno.rst.txt | 25 Juno supports CPU, cluster and system power down states, corresponding to power
110 last CPUs in their respective clusters to power down, therefore both the L1 and
141 effectively serializes the SCP power down commands from all CPUs.
143 On platforms with a more efficient CPU power down mechanism, it should be
172 are large because all other CPUs in the cluster are powered down during the
173 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
181 CPU 4 continues to run while CPU 5 is suspended. Hence CPU 5 only powers down to
242 CPUs in that cluster are powerered down during the test. The ``CPU_OFF`` call
243 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
246 lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
|
| /trusted-firmware-a/docs/perf/ |
| A D | psci-performance-juno.rst | 25 Juno supports CPU, cluster and system power down states, corresponding to power
110 last CPUs in their respective clusters to power down, therefore both the L1 and
141 effectively serializes the SCP power down commands from all CPUs.
143 On platforms with a more efficient CPU power down mechanism, it should be
172 are large because all other CPUs in the cluster are powered down during the
173 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
181 CPU 4 continues to run while CPU 5 is suspended. Hence CPU 5 only powers down to
242 CPUs in that cluster are powerered down during the test. The ``CPU_OFF`` call
243 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
246 lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
|
| /trusted-firmware-a/drivers/renesas/common/ddr/ddr_b/ |
| A D | boot_init_dram_config.c | 1890 uint32_t dataL, down, up; in opencheck_SSI_WS6() local
1914 down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; in opencheck_SSI_WS6()
1932 if (down == up) { in opencheck_SSI_WS6()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_static/css/ |
| A D | badge_only.css | 1 …e}.fa-book:before,.icon-book:before{content:"\f02d"}.fa-caret-down:before,.icon-caret-down:before{…
|
| A D | theme.css | 4 …down:before{content:""}.fa-arrow-circle-o-up:before{content:""}.fa-inbox:before{content:""}.fa-…
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| /trusted-firmware-a/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 68 whether the PSCI API resulted in power down of the CPU.
79 be preserved across CPU power down/power up cycles are maintained in
95 ``cpu_context_t`` is stripped down for just PSCI CPU context management.
264 caller if PSCI API causes power down of the CPU. In this case, when the CPU
276 `PSCI spec`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
462 appropriately during CPU power down/power up. Any secure interrupt targeted
464 to power down of the current CPU. During power up, these interrupt can be
492 The ``svc_suspend`` callback is called during power down bu either
496 (first parameter) denotes the highest power domain level being powered down
526 The CPU operations (cpu_ops) framework implement power down sequence specific
|
| A D | porting-guide.rst | 153 Defines the local power state corresponding to the deepest power down
165 PSCI implementation to distinguish between retention and power down local
173 power domain level (power-down and retention). If the platform needs to
1032 present) during a cluster power down sequence. The default weak implementation
1033 doesn't do anything. Since this API is called during the power down sequence,
2236 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2383 power down state where as it could be either power down, retention or run state
2393 calls this function when suspending to a power down state, and it guarantees
2398 power down state and it is safe to perform some or all of the platform
2442 data, for example in DRAM. The Distributor can then be powered down using an
[all …]
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | psci-lib-integration-guide.rst.txt | 68 whether the PSCI API resulted in power down of the CPU.
79 be preserved across CPU power down/power up cycles are maintained in
95 ``cpu_context_t`` is stripped down for just PSCI CPU context management.
264 caller if PSCI API causes power down of the CPU. In this case, when the CPU
276 `PSCI spec`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
462 appropriately during CPU power down/power up. Any secure interrupt targeted
464 to power down of the current CPU. During power up, these interrupt can be
492 The ``svc_suspend`` callback is called during power down bu either
496 (first parameter) denotes the highest power domain level being powered down
526 The CPU operations (cpu_ops) framework implement power down sequence specific
|
| A D | porting-guide.rst.txt | 153 Defines the local power state corresponding to the deepest power down
165 PSCI implementation to distinguish between retention and power down local
173 power domain level (power-down and retention). If the platform needs to
1032 present) during a cluster power down sequence. The default weak implementation
1033 doesn't do anything. Since this API is called during the power down sequence,
2236 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2383 power down state where as it could be either power down, retention or run state
2393 calls this function when suspending to a power down state, and it guarantees
2398 power down state and it is safe to perform some or all of the platform
2442 data, for example in DRAM. The Distributor can then be powered down using an
[all …]
|
| /trusted-firmware-a/plat/allwinner/common/ |
| A D | arisc_off.S | 76 reset: l.sw 0x1c00(r13),r0 # pull down our own reset line
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/about/ |
| A D | features.rst.txt | 17 - Library support for CPU specific reset and power down sequences. This
|
| /trusted-firmware-a/docs/about/ |
| A D | features.rst | 17 - Library support for CPU specific reset and power down sequences. This
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | romlib-design.rst.txt | 122 This will have for effect to shift down all the BL images by 1 page.
|
| A D | xlat-tables-lib-v2-design.rst.txt | 85 The granularity controls the translation table level to go down to when mapping
|
| /trusted-firmware-a/docs/components/ |
| A D | romlib-design.rst | 122 This will have for effect to shift down all the BL images by 1 page.
|
| A D | xlat-tables-lib-v2-design.rst | 85 The granularity controls the translation table level to go down to when mapping
|
| /trusted-firmware-a/docs/design/ |
| A D | firmware-design.rst | 1353 #. Processor specific power down sequences.
1365 #. allows each processor to implement the power down sequence mandated in
1387 ``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1417 CPU specific power down sequence
1422 retrieved during power down sequences.
1424 Various CPU drivers register handlers to perform power down at certain power
1425 levels for that specific CPU. The PSCI service, upon receiving a power down
1426 request, determines the highest power level at which to execute power down
1428 pick the right power down handler for the requested level. The function
1436 turning off CCI coherency during a cluster power down.
[all …]
|
| A D | cpu-specific-build-macros.rst | 478 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
481 is a known safe deviation from the Cortex-A57 TRM defined power down
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | firmware-design.rst.txt | 1353 #. Processor specific power down sequences.
1365 #. allows each processor to implement the power down sequence mandated in
1387 ``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1417 CPU specific power down sequence
1422 retrieved during power down sequences.
1424 Various CPU drivers register handlers to perform power down at certain power
1425 levels for that specific CPU. The PSCI service, upon receiving a power down
1426 request, determines the highest power level at which to execute power down
1428 pick the right power down handler for the requested level. The function
1436 turning off CCI coherency during a cluster power down.
[all …]
|
| A D | cpu-specific-build-macros.rst.txt | 478 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
481 is a known safe deviation from the Cortex-A57 TRM defined power down
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | change-log.md.txt | 1803 - Support for powering down CPUs during CPU suspend has been removed
2117 - xilinx: versal: Implement power down/restart related EEMI, SMC handler for
2248 - ti: k3: common: Enable ARM cluster power down and rename device IDs to be
3330 power-down state and with data caches enabled.
3563 - Skip performing cache maintenance during power-up and power-down.
3570 (DSU). The power-down and power-up sequences are therefore mostly managed in
3770 threads which might need powering down individually.
3999 - Enabled processor power-down and automatic power-on using GICv3.
4384 - Added support for CPU specific reset sequences, power down sequences and
4485 suspending a CPU. This allows platforms that implement multiple power-down
[all …]
|
| /trusted-firmware-a/docs/ |
| A D | change-log.md | 1803 - Support for powering down CPUs during CPU suspend has been removed
2117 - xilinx: versal: Implement power down/restart related EEMI, SMC handler for
2248 - ti: k3: common: Enable ARM cluster power down and rename device IDs to be
3330 power-down state and with data caches enabled.
3563 - Skip performing cache maintenance during power-up and power-down.
3570 (DSU). The power-down and power-up sequences are therefore mostly managed in
3770 threads which might need powering down individually.
3999 - Enabled processor power-down and automatic power-on using GICv3.
4384 - Added support for CPU specific reset sequences, power down sequences and
4485 suspending a CPU. This allows platforms that implement multiple power-down
[all …]
|
| /trusted-firmware-a/docs/build/TF-A_2.5/ |
| A D | searchindex.js | 1 …down:[2,6,26,34,37,48,53,55,63,119],downgrad:6,download:[32,70,73,78,79,86,107,119,123],downstream…
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| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.log | 918 lled dur-ing power down bu ei-ther PSCI_SUSPEND or
|