/trusted-firmware-a/bl32/tsp/ |
A D | tsp_interrupt.c | 30 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) in tsp_update_sync_sel1_intr_stats() argument 41 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
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A D | tsp_private.h | 100 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
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/trusted-firmware-a/plat/nvidia/tegra/common/ |
A D | tegra_fiq_glue.c | 66 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler() 139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
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/trusted-firmware-a/services/std_svc/sdei/ |
A D | sdei_intr_mgmt.c | 40 uint64_t elr_el3; member 176 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx() 196 write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3); in restore_event_ctx() 330 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch() 736 write_elr_el2(disp_ctx->elr_el3); in sdei_event_complete() 740 write_elr_el1(disp_ctx->elr_el3); in sdei_event_complete()
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/trusted-firmware-a/plat/nvidia/tegra/include/drivers/ |
A D | tegra_gic.h | 17 uint64_t elr_el3; member
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/trusted-firmware-a/bl2/aarch64/ |
A D | bl2_run_next_image.S | 37 msr elr_el3, x0
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/trusted-firmware-a/lib/cpus/aarch64/ |
A D | wa_cve_2017_5715_bpiall.S | 58 mrs x7, elr_el3 85 msr elr_el3, x11 277 msr elr_el3, x7
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A D | neoverse_n1.S | 646 mrs x3, elr_el3 648 msr elr_el3, x3
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/trusted-firmware-a/bl1/aarch64/ |
A D | bl1_entrypoint.S | 100 msr elr_el3, x0
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A D | bl1_exceptions.S | 182 msr elr_el3, x0 271 mrs x17, elr_el3
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/trusted-firmware-a/bl31/aarch64/ |
A D | runtime_exceptions.S | 222 mrs x1, elr_el3 498 mrs x17, elr_el3 605 mrs x4, elr_el3
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A D | ea_delegate.S | 246 mrs x3, elr_el3 299 msr elr_el3, x2
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A D | crash_reporting.S | 399 mrs x15, elr_el3
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/trusted-firmware-a/plat/qti/qtiseclib/inc/ |
A D | qtiseclib_defs.h | 77 uint64_t elr_el3; member
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/trusted-firmware-a/plat/nxp/common/sip_svc/aarch64/ |
A D | sipsvc.S | 56 msr elr_el3, x1
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/trusted-firmware-a/plat/hisilicon/hikey/aarch64/ |
A D | hikey_helpers.S | 117 mrs x4, elr_el3
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/trusted-firmware-a/plat/hisilicon/hikey960/aarch64/ |
A D | hikey960_helpers.S | 121 mrs x4, elr_el3
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/trusted-firmware-a/plat/qti/qtiseclib/src/ |
A D | qtiseclib_cb_interface.c | 142 qti_ns_ctx->elr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_ELR_EL3); in qtiseclib_cb_get_ns_ctx()
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/trusted-firmware-a/plat/renesas/common/aarch64/ |
A D | plat_helpers.S | 190 msr elr_el3, x0
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/trusted-firmware-a/include/arch/aarch64/ |
A D | arch_helpers.h | 264 DEFINE_SYSREG_RW_FUNCS(elr_el3) in DEFINE_SYSREG_READ_FUNC()
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/trusted-firmware-a/lib/el3_runtime/aarch64/ |
A D | context.S | 912 msr elr_el3, x17
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/trusted-firmware-a/build/qemu/release/bl31/ |
A D | bl31.dump | 1520 e0409c4: d53e4023 mrs x3, elr_el3 1536 e040a04: d51e4022 msr elr_el3, x2 1657 e040bd0: d51e4031 msr elr_el3, x17 2067 e0410e0: d53e4031 mrs x17, elr_el3 4053 e042cd8: d53e4023 mrs x3, elr_el3 7254 e0464a4: d53e4021 mrs x1, elr_el3 7287 e046524: d53e4021 mrs x1, elr_el3 7349 e0466a4: d53e4021 mrs x1, elr_el3 7382 e046724: d53e4021 mrs x1, elr_el3
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/trusted-firmware-a/build/qemu/release/bl1/ |
A D | bl1.dump | 2939 2260: d51e4020 msr elr_el3, x0 2970 22cc: d53e4031 mrs x17, elr_el3 3229 2648: d51e4031 msr elr_el3, x17
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/trusted-firmware-a/docs/design/ |
A D | interrupt-framework-design.rst | 788 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
A D | interrupt-framework-design.rst.txt | 788 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
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