| /trusted-firmware-a/docs/design/ |
| A D | cpu-specific-build-macros.rst | 64 for it to specify which errata workarounds should be enabled or not.
72 CPU. This needs to be enabled for all revisions of the CPU.
116 r0p4 and onwards, this errata is enabled by default in hardware.
136 CPU. This needs to be enabled only for revision r0p0 of the CPU.
139 CPU. This needs to be enabled only for revision r0p0 of the CPU.
142 CPU. This needs to be enabled only for revision r0p0 of the CPU.
159 CPU. This needs to be enabled only for revision r0p0 of the CPU.
282 CPU. This needs to be enabled for revisions r0p0 and r1p0.
475 architecture that can be enabled by the platform as desired.
492 <= r0p3 of the CPU and is enabled by default.
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | cpu-specific-build-macros.rst.txt | 64 for it to specify which errata workarounds should be enabled or not.
72 CPU. This needs to be enabled for all revisions of the CPU.
116 r0p4 and onwards, this errata is enabled by default in hardware.
136 CPU. This needs to be enabled only for revision r0p0 of the CPU.
139 CPU. This needs to be enabled only for revision r0p0 of the CPU.
142 CPU. This needs to be enabled only for revision r0p0 of the CPU.
159 CPU. This needs to be enabled only for revision r0p0 of the CPU.
282 CPU. This needs to be enabled for revisions r0p0 and r1p0.
475 architecture that can be enabled by the platform as desired.
492 <= r0p3 of the CPU and is enabled by default.
[all …]
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| /trusted-firmware-a/plat/marvell/armada/a3k/common/ |
| A D | dram_win.c | 46 uint32_t enabled; member
189 uint32_t base_reg, ctrl_reg, size_reg, enabled, target; in dram_win_map_build() local
196 enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE; in dram_win_map_build()
198 if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM)) in dram_win_map_build()
233 if (!win_cfg->enabled) in cpu_win_set()
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| /trusted-firmware-a/plat/layerscape/common/ |
| A D | ls_tzc380.c | 17 unsigned int enabled, unsigned int low_addr, in tzc380_set_region() argument
41 ((size & 0x3F) << 1) | (enabled & 0x1); in tzc380_set_region()
68 tzc380_reg_list[reg_id].enabled, in tzc380_setup()
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| /trusted-firmware-a/plat/st/stm32mp1/ |
| A D | stm32mp1_scmi.c | 32 bool enabled; member
76 .enabled = _init_enabled, \
307 return (int32_t)clock->enabled; in plat_scmi_clock_get_state()
324 if (!clock->enabled) { in plat_scmi_clock_set_state()
327 clock->enabled = true; in plat_scmi_clock_set_state()
330 if (clock->enabled) { in plat_scmi_clock_set_state()
333 clock->enabled = false; in plat_scmi_clock_set_state()
462 if (clk->enabled && in stm32mp1_init_scmi_server()
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| /trusted-firmware-a/plat/arm/common/ |
| A D | arm_nor_psci_mem_protect.c | 38 int arm_psci_read_mem_protect(int *enabled) in arm_psci_read_mem_protect() argument
43 *enabled = (tmp == 1) ? 1 : 0; in arm_psci_read_mem_protect()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | mpmm.rst.txt | 11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
28 |AMU| counters that make up the |MPMM| gears must be enabled by the EL3
|
| A D | realm-management-extension.rst.txt | 45 enabled, TF-A runs in the Root world at EL3. Therefore, the boot flow is
46 modified to run BL2 at EL3 when RME is enabled. In addition to this, a
50 The boot flow when RME is enabled looks like the following:
55 4. BL31 initializes SPM (if SPM is enabled)
80 and the interface between R-EL2 and EL3. When building TF-A with RME enabled,
87 This section describes how you can build and run TF-A with RME enabled.
164 Build TF-A with RME as well as SPM enabled.
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| /trusted-firmware-a/docs/components/ |
| A D | mpmm.rst | 11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
28 |AMU| counters that make up the |MPMM| gears must be enabled by the EL3
|
| A D | realm-management-extension.rst | 45 enabled, TF-A runs in the Root world at EL3. Therefore, the boot flow is
46 modified to run BL2 at EL3 when RME is enabled. In addition to this, a
50 The boot flow when RME is enabled looks like the following:
55 4. BL31 initializes SPM (if SPM is enabled)
80 and the interface between R-EL2 and EL3. When building TF-A with RME enabled,
87 This section describes how you can build and run TF-A with RME enabled.
164 Build TF-A with RME as well as SPM enabled.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/fconf/ |
| A D | amu-bindings.rst.txt | 67 | | | | be enabled prior to EL3 exit. |
140 defined by ``amu1``. This will cause ``counterX`` and ``counterY`` to be enabled
141 for both ``cpu0`` and ``cpu1``, and ``counterZ`` to be enabled for both ``cpu2``
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| /trusted-firmware-a/docs/components/fconf/ |
| A D | amu-bindings.rst | 67 | | | | be enabled prior to EL3 exit. |
140 defined by ``amu1``. This will cause ``counterX`` and ``counterY`` to be enabled
141 for both ``cpu0`` and ``cpu1``, and ``counterZ`` to be enabled for both ``cpu2``
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| /trusted-firmware-a/docs/getting_started/ |
| A D | build-options.rst | 59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
124 Note that Pointer Authentication is enabled for Non-secure world
155 this is only enabled for a debug build of the firmware.
170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and
209 flag has to be enabled. 0 is the default.
304 registers so are enabled together. Using this option without
333 systems that have SPM_MM enabled.
444 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
643 cannot be enabled when the ``SPM_MM`` option is enabled.
662 enabled (``SPD=spmd``).
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | build-options.rst.txt | 59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
124 Note that Pointer Authentication is enabled for Non-secure world
155 this is only enabled for a debug build of the firmware.
170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and
209 flag has to be enabled. 0 is the default.
304 registers so are enabled together. Using this option without
333 systems that have SPM_MM enabled.
444 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
643 cannot be enabled when the ``SPM_MM`` option is enabled.
662 enabled (``SPD=spmd``).
[all …]
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| /trusted-firmware-a/plat/layerscape/board/ls1043/include/ |
| A D | soc_tzasc.h | 61 unsigned int enabled; member
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| /trusted-firmware-a/lib/mpmm/ |
| A D | mpmm.mk | 12 $(error MPMM support (`ENABLE_MPMM`) can only be enabled in AArch64 images (`ARCH`))
|
| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-2.rst | 43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
45 secure privileged invasive debug is enabled by the authentication interface, at
|
| A D | security-advisory-tfv-7.rst | 40 world execution. The mitigation is enabled by setting an implementation defined
46 The mitigation code is enabled by default, but can be disabled at compile time
88 the default mitigation state for firmware-managed execution contexts is enabled.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-2.rst.txt | 43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
45 secure privileged invasive debug is enabled by the authentication interface, at
|
| A D | security-advisory-tfv-7.rst.txt | 40 world execution. The mitigation is enabled by setting an implementation defined
46 The mitigation code is enabled by default, but can be disabled at compile time
88 the default mitigation state for firmware-managed execution contexts is enabled.
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| /trusted-firmware-a/docs/plat/marvell/armada/misc/ |
| A D | mvebu-iob.rst | 10 the enabled windows. If there is a hit and it passes the security checks, it is
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/misc/ |
| A D | mvebu-iob.rst.txt | 10 the enabled windows. If there is a hit and it passes the security checks, it is
|
| /trusted-firmware-a/docs/process/ |
| A D | security-hardening.rst | 139 and ``Wvla`` flags are enabled.
142 ``Wpacked-bitfield-compat`` are GCC specific flags that are also enabled.
164 NB: The ``Werror`` flag is enabled by default in TF-A and can be disabled by
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/process/ |
| A D | security-hardening.rst.txt | 139 and ``Wvla`` flags are enabled.
142 ``Wpacked-bitfield-compat`` are GCC specific flags that are also enabled.
164 NB: The ``Werror`` flag is enabled by default in TF-A and can be disabled by
|
| /trusted-firmware-a/docs/perf/ |
| A D | performance-monitoring-unit.rst | 49 the counters are enabled (permitted to increment) via the ``PMCNTENSET`` and
122 security state unless it is enabled here.
|