Searched refs:g1_ffe_cap_sel (Results 1 – 6 of 6) sorted by relevance
| /trusted-firmware-a/plat/marvell/octeontx/otx2/t91/t9130/board/ |
| A D | phy-porting-layer.h | 23 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
34 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
51 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
63 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
80 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
91 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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| /trusted-firmware-a/plat/marvell/armada/a8k/a80x0/board/ |
| A D | phy-porting-layer.h | 21 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
30 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
45 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
54 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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| /trusted-firmware-a/drivers/marvell/comphy/ |
| A D | phy-default-porting-layer.h | 19 .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
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| A D | phy-comphy-cp110.h | 14 uint8_t g1_ffe_cap_sel; member
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| A D | phy-comphy-cp110.c | 863 xfi_static_values->g1_ffe_cap_sel, in mvebu_cp110_comphy_xfi_power_on()
1103 data |= xfi_static_values->g1_ffe_cap_sel << in mvebu_cp110_comphy_xfi_power_on()
2137 uint32_t g1_ffe_cap_sel, g1_ffe_res_sel, align90, g1_dfe_res; in mvebu_cp110_comphy_xfi_rx_training() local
2213 g1_ffe_cap_sel = ((mmio_read_32(hpipe_addr + in mvebu_cp110_comphy_xfi_rx_training()
2229 g1_ffe_res_sel, g1_ffe_cap_sel, align90, g1_dfe_res); in mvebu_cp110_comphy_xfi_rx_training()
2247 data = g1_ffe_cap_sel << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2278 printf("\t.g1_ffe_cap_sel = 0x%x,\n", g1_ffe_cap_sel); in mvebu_cp110_comphy_xfi_rx_training()
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| /trusted-firmware-a/plat/marvell/armada/a8k/a70x0_mochabin/board/ |
| A D | phy-porting-layer.h | 25 { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x60,
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