Searched refs:get_el1_sysregs_ctx (Results 1 – 7 of 7) sorted by relevance
| /trusted-firmware-a/services/std_svc/spm_mm/ |
| A D | spm_mm_setup.c | 124 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1, in spm_sp_setup()
127 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1, in spm_sp_setup()
130 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1, in spm_sp_setup()
134 u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1); in spm_sp_setup()
170 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); in spm_sp_setup()
178 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1, in spm_sp_setup()
181 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, in spm_sp_setup()
191 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CPACR_EL1, in spm_sp_setup()
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| /trusted-firmware-a/lib/el3_runtime/aarch64/ |
| A D | context_mgmt.c | 335 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); in cm_setup_context()
345 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); in cm_setup_context()
492 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), in cm_prepare_el3_exit()
752 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); in cm_el1_sysregs_context_save()
769 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); in cm_el1_sysregs_context_restore()
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| /trusted-firmware-a/plat/qti/qtiseclib/src/ |
| A D | qtiseclib_cb_interface.c | 145 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SPSR_EL1); in qtiseclib_cb_get_ns_ctx()
147 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_ELR_EL1); in qtiseclib_cb_get_ns_ctx()
148 qti_ns_ctx->sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SP_EL1); in qtiseclib_cb_get_ns_ctx()
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| /trusted-firmware-a/plat/nvidia/tegra/common/ |
| A D | tegra_fiq_glue.c | 131 const el1_sysregs_t *el1state_ctx = get_el1_sysregs_ctx(ctx); in tegra_fiq_get_intr_context()
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| /trusted-firmware-a/services/spd/trusty/ |
| A D | trusty.c | 163 ctx->fiq_sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1); in trusty_fiq_handler()
165 write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp); in trusty_fiq_handler()
224 write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1); in trusty_fiq_exit()
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
| A D | plat_psci_handlers.c | 359 actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1)); in tegra_soc_pwr_domain_on_finish()
362 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); in tegra_soc_pwr_domain_on_finish()
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| /trusted-firmware-a/include/lib/el3_runtime/aarch64/ |
| A D | context.h | 436 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) macro
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