| /trusted-firmware-a/plat/mediatek/common/drivers/gic600/ |
| A D | mt_gic_v3.c | 37 .gicr_base = MT_GIC_RDIST_BASE,
80 uintptr_t gicr_base; in mt_gic_rdistif_init() local
91 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
98 uintptr_t gicr_base; in mt_gic_rdistif_save() local
115 uintptr_t gicr_base; in mt_gic_rdistif_restore() local
125 mmio_write_32(gicr_base + GICR_IGRPMODR0, in mt_gic_rdistif_restore()
133 uintptr_t gicr_base; in mt_gic_rdistif_restore_all() local
142 mmio_write_32(gicr_base + GICR_IGRPMODR0, in mt_gic_rdistif_restore_all()
150 uintptr_t gicr_base; in gic_sgi_save_all() local
162 uintptr_t gicr_base; in gic_sgi_restore_all() local
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| /trusted-firmware-a/drivers/arm/gic/v3/ |
| A D | arm_gicv3_common.c | 30 uintptr_t gicr_base = 0; in arm_gicv3_distif_pre_save() local
42 assert(gicr_base); in arm_gicv3_distif_pre_save()
43 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); in arm_gicv3_distif_pre_save()
44 assert(gicr_read_waker(gicr_base) & WAKER_PS_BIT); in arm_gicv3_distif_pre_save()
61 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_SL_BIT); in arm_gicv3_distif_pre_save()
74 uintptr_t gicr_base; in arm_gicv3_distif_post_restore() local
85 assert(gicr_base); in arm_gicv3_distif_post_restore()
93 if (!(gicr_read_waker(gicr_base) & WAKER_SL_BIT)) in arm_gicv3_distif_post_restore()
102 assert(gicr_read_waker(gicr_base) & WAKER_QSC_BIT); in arm_gicv3_distif_post_restore()
105 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_SL_BIT); in arm_gicv3_distif_post_restore()
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| A D | gicv3_helpers.c | 31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); in gicv3_rdistif_mark_core_awake()
45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); in gicv3_rdistif_mark_core_asleep()
59 uintptr_t gicr_base, in gicv3_rdistif_base_addrs_probe() argument
65 uintptr_t rdistif_base = gicr_base; in gicv3_rdistif_base_addrs_probe()
277 gicr_write_icenabler(gicr_base, i, ~0U); in gicv3_ppi_sgi_config_defaults()
281 gicr_wait_for_pending_write(gicr_base); in gicv3_ppi_sgi_config_defaults()
286 gicr_write_igroupr(gicr_base, i, ~0U); in gicv3_ppi_sgi_config_defaults()
300 gicr_write_icfgr(gicr_base, i, 0U); in gicv3_ppi_sgi_config_defaults()
331 gicr_clr_igroupr(gicr_base, intr_num); in gicv3_secure_ppi_sgi_config_props()
338 gicr_set_igrpmodr(gicr_base, intr_num); in gicv3_secure_ppi_sgi_config_props()
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| A D | gic-x00.c | 107 uintptr_t gicr_base; in get_gicr_base() local
113 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in get_gicr_base()
114 assert(gicr_base != 0UL); in get_gicr_base()
116 return gicr_base; in get_gicr_base()
121 uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR); in gicv3_redists_need_power_mgmt()
150 uintptr_t gicr_base = get_gicr_base(proc_num); in gicv3_rdistif_off() local
153 if (gicv3_redists_need_power_mgmt(gicr_base)) { in gicv3_rdistif_off()
154 gic600_pwr_off(gicr_base); in gicv3_rdistif_off()
165 uintptr_t gicr_base = get_gicr_base(proc_num); in gicv3_rdistif_on() local
168 if (gicv3_redists_need_power_mgmt(gicr_base)) { in gicv3_rdistif_on()
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| A D | gicv3_main.c | 224 uintptr_t gicr_base; in gicv3_rdistif_init() local
242 assert(gicr_base != 0U); in gicv3_rdistif_init()
274 uintptr_t gicr_base; in gicv3_cpuif_enable() local
339 uintptr_t gicr_base; in gicv3_cpuif_disable() local
367 assert(gicr_base != 0U); in gicv3_cpuif_disable()
421 uintptr_t gicr_base; in gicv3_get_interrupt_type() local
543 uintptr_t gicr_base; in gicv3_rdistif_save() local
618 uintptr_t gicr_base; in gicv3_rdistif_init_restore() local
666 gicr_write_ctlr(gicr_base, in gicv3_rdistif_init_restore()
1011 uintptr_t gicr_base; in gicv3_set_interrupt_priority() local
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| A D | gicv3_private.h | 239 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
240 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
248 uintptr_t gicr_base,
250 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
251 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
343 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) in gicr_wait_for_pending_write() argument
345 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { in gicr_wait_for_pending_write()
349 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) in gicr_wait_for_upstream_pending_write() argument
351 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { in gicr_wait_for_upstream_pending_write()
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| /trusted-firmware-a/plat/mediatek/mt8183/ |
| A D | plat_mt_gic.c | 34 .gicr_base = MT_GIC_RDIST_BASE,
85 uintptr_t gicr_base; in mt_gic_rdistif_init() local
88 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_init()
91 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); in mt_gic_rdistif_init()
92 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); in mt_gic_rdistif_init()
96 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
113 uintptr_t gicr_base; in mt_gic_rdistif_save() local
116 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_save()
120 gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0); in mt_gic_rdistif_save()
121 gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1); in mt_gic_rdistif_save()
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| /trusted-firmware-a/plat/arm/board/arm_fpga/ |
| A D | fpga_gicv3.c | 43 uintptr_t gicr_base = 0U; in plat_fpga_gic_init() local
77 frame_id = gicv3_get_component_partnum(gicr_base); in plat_fpga_gic_init()
81 nr_itses, (unsigned long long)gicr_base); in plat_fpga_gic_init()
88 gicr_base = 0U; in plat_fpga_gic_init()
97 its_typer = mmio_read_64(gicr_base + GITS_TYPER); in plat_fpga_gic_init()
99 gicr_base += 4U << 16; in plat_fpga_gic_init()
101 gicr_base += 2U << 16; in plat_fpga_gic_init()
111 if (gicr_base == 0U) { in plat_fpga_gic_init()
113 &fpga_gicv3_driver_data.gicr_base, in plat_fpga_gic_init()
120 fpga_gicv3_driver_data.gicr_base = gicr_base; in plat_fpga_gic_init()
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| /trusted-firmware-a/plat/ti/k3/common/ |
| A D | k3_gicv3.c | 45 uintptr_t gicr_base = 0; in k3_gic_driver_init() local
52 gicr_base = gicr_check; in k3_gic_driver_init()
57 assert(gicr_base != 0); in k3_gic_driver_init()
66 k3_gic_data.gicr_base = gicr_base; in k3_gic_driver_init()
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| /trusted-firmware-a/plat/socionext/uniphier/ |
| A D | uniphier_gicv3.c | 62 .gicr_base = 0x5fe40000,
71 .gicr_base = 0x5fe80000,
80 .gicr_base = 0x5fe80000,
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| /trusted-firmware-a/common/ |
| A D | fdt_fixup.c | 420 uintptr_t gicr_base, unsigned int gicr_frame_size) in fdt_adjust_gic_redist() argument
443 if (gicr_base != INVALID_BASE_ADDR) { in fdt_adjust_gic_redist()
445 reg_32 = cpu_to_fdt32(gicr_base); in fdt_adjust_gic_redist()
448 reg_64 = cpu_to_fdt64(gicr_base); in fdt_adjust_gic_redist()
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| /trusted-firmware-a/include/common/ |
| A D | fdt_fixup.h | 18 int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base,
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| /trusted-firmware-a/plat/qemu/common/ |
| A D | qemu_gicv3.c | 26 .gicr_base = GICR_BASE,
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| /trusted-firmware-a/plat/nvidia/tegra/common/ |
| A D | tegra_gicv3.c | 41 tegra_gic_data.gicr_base = TEGRA_GICR_BASE; in tegra_gic_setup()
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| /trusted-firmware-a/plat/brcm/common/ |
| A D | brcm_gicv3.c | 44 .gicr_base = PLAT_BRCM_GICR_BASE,
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| /trusted-firmware-a/plat/rockchip/common/ |
| A D | rockchip_gicv3.c | 40 .gicr_base = PLAT_RK_GICR_BASE,
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| /trusted-firmware-a/drivers/nxp/gic/ |
| A D | ls_gicv3.c | 26 ls_gic_data.gicr_base = nxp_gicr_addr; in plat_ls_gic_driver_init()
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| /trusted-firmware-a/plat/arm/board/fvp/include/ |
| A D | fconf_hw_config_getter.h | 20 uint64_t gicr_base; member
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| /trusted-firmware-a/plat/socionext/synquacer/ |
| A D | sq_gicv3.c | 61 .gicr_base = PLAT_SQ_GICR_BASE,
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| /trusted-firmware-a/plat/xilinx/versal/ |
| A D | versal_gicv3.c | 64 .gicr_base = PLAT_VERSAL_GICR_BASE,
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| /trusted-firmware-a/plat/marvell/armada/common/ |
| A D | marvell_gicv3.c | 66 .gicr_base = PLAT_MARVELL_GICR_BASE,
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| /trusted-firmware-a/plat/imx/common/ |
| A D | plat_imx8_gic.c | 38 .gicr_base = PLAT_GICR_BASE,
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| /trusted-firmware-a/plat/arm/board/fvp/ |
| A D | fvp_gicv3.c | 112 gicr_base); in plat_arm_gic_driver_init()
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| /trusted-firmware-a/plat/arm/common/ |
| A D | arm_gicv3.c | 79 .gicr_base = 0U,
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| /trusted-firmware-a/plat/qti/common/src/ |
| A D | qti_gic_v3.c | 89 .gicr_base = QTI_GICR_BASE,
|