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/trusted-firmware-a/lib/zlib/
A Dinflate.c509 have--; \
652 in = have;
759 if (copy > have) copy = have;
791 have -= copy;
906 if (copy > have) copy = have;
936 state->have = 0;
957 state->have = 0;
1378 unsigned FAR *have; in syncsearch()
1385 got = *have;
1396 *have = got;
[all …]
A Dinflate.h117 unsigned have; /* number of code lengths in lens[] */ member
A Dzlib.h1818 unsigned have; member
1826 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
1829 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
/trusted-firmware-a/docs/plat/
A Dnvidia-tegra.rst25 including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
26 Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
63 including legacy Armv7-A applications. The Cortex-A57 processors each have
64 48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
66 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
100 the scatter file to be used. Tegra platforms have verified BL31 image generation
A Drpi4.rst10 as well, but have not been tested at this point.
29 ``config.txt``. You should have AArch64 code in the file loaded as the
73 memory. The load addresses have a default, but can also be changed by
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/
A Dnvidia-tegra.rst.txt25 including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
26 Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
63 including legacy Armv7-A applications. The Cortex-A57 processors each have
64 48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
66 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
100 the scatter file to be used. Tegra platforms have verified BL31 image generation
A Drpi4.rst.txt10 as well, but have not been tested at this point.
29 ``config.txt``. You should have AArch64 code in the file loaded as the
73 memory. The load addresses have a default, but can also be changed by
/trusted-firmware-a/
A Ddco.txt18 have the right to submit it under the open source license
23 license and I have the right under that license to submit that
30 person who certified (a), (b) or (c) and I have not modified
/trusted-firmware-a/docs/build/TF-A_2.5/_downloads/64c40a63b9b2c30373557926065e7bb2/
A Ddco.txt18 have the right to submit it under the open source license
23 license and I have the right under that license to submit that
30 person who certified (a), (b) or (c) and I have not modified
/trusted-firmware-a/docs/design/
A Dpsci-pd-tree.rst54 ``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
59 where the power domain tree does not have a single root node, for example,
74 above text further. The leaf and non-leaf nodes in this tree have been numbered
132 platform API have changed since it is required to validate the passed MPIDR. It
156 contiguous or certain cores have been disabled. This essentially means that the
157 MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
178 To fulfill requirement 3 and 4, separate data structures have been defined
200 * -> cpu_start_idx + ncpus' have this node as their parent.
243 node. Other fields have been ignored for simplicity.
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/
A Dpsci-pd-tree.rst.txt54 ``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
59 where the power domain tree does not have a single root node, for example,
74 above text further. The leaf and non-leaf nodes in this tree have been numbered
132 platform API have changed since it is required to validate the passed MPIDR. It
156 contiguous or certain cores have been disabled. This essentially means that the
157 MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
178 To fulfill requirement 3 and 4, separate data structures have been defined
200 * -> cpu_start_idx + ncpus' have this node as their parent.
243 node. Other fields have been ignored for simplicity.
/trusted-firmware-a/docs/process/
A Dcode-review-guidelines.rst33 to different timescales, and have different priorities. Keep this in
65 - If there is only one code owner and they have become unresponsive, ask one
73 directory to have the freedom to change it in any way. This way, your changes
80 There are no good or bad review comments. If you have any doubt about a patch or
128 through the ``Code-Owner-Review+1`` label in Gerrit. If instead, they have
178 - New files must have the correct license and copyright headers. See :ref:`this
203 - Before merging a patch, verify that all review comments have been addressed.
208 through the ``Maintainer-Review+1`` label in Gerrit. If instead, they have
A Dfaq.rst24 they follow the coding guidelines, have already had some code review, and have
48 time. In simple cases where all potential regressions have already been tested,
A Dcommit-style.rst18 - What impact does it have?
83 file are organized by their changelog section, each of which may have one or
102 are adding a new component that does not yet have a designated scope, please
148 Ensure that each commit also has a unique ``Change-Id:`` line. If you have
A Dsecurity.rst24 If you think you have found a security vulnerability, please **do not**
29 TF-A have a chance to consider the implications of the vulnerability and its
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/process/
A Dcode-review-guidelines.rst.txt33 to different timescales, and have different priorities. Keep this in
65 - If there is only one code owner and they have become unresponsive, ask one
73 directory to have the freedom to change it in any way. This way, your changes
80 There are no good or bad review comments. If you have any doubt about a patch or
128 through the ``Code-Owner-Review+1`` label in Gerrit. If instead, they have
178 - New files must have the correct license and copyright headers. See :ref:`this
203 - Before merging a patch, verify that all review comments have been addressed.
208 through the ``Maintainer-Review+1`` label in Gerrit. If instead, they have
A Dfaq.rst.txt24 they follow the coding guidelines, have already had some code review, and have
48 time. In simple cases where all potential regressions have already been tested,
A Dcommit-style.rst.txt18 - What impact does it have?
83 file are organized by their changelog section, each of which may have one or
102 are adding a new component that does not yet have a designated scope, please
148 Ensure that each commit also has a unique ``Change-Id:`` line. If you have
A Dsecurity.rst.txt24 If you think you have found a security vulnerability, please **do not**
29 TF-A have a chance to consider the implications of the vulnerability and its
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/about/
A Dcontact.rst.txt8 If you think you have found a security vulnerability, please report this using
46 Arm licensees have an additional support conduit - they may contact Arm directly
/trusted-firmware-a/docs/about/
A Dcontact.rst8 If you think you have found a security vulnerability, please report this using
46 Arm licensees have an additional support conduit - they may contact Arm directly
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/threat_model/
A Dindex.rst.txt8 using a data flow diagram. Then we provide a list of threats we have identified
/trusted-firmware-a/docs/threat_model/
A Dindex.rst8 using a data flow diagram. Then we provide a list of threats we have identified
/trusted-firmware-a/docs/design_documents/
A Dcmake_framework.rst96 generation or dtc for device tree compilation. These tools have to be found
108 In the provisioning phase, first we have to obtain the necessary resources, i.e.
109 clone the code repository and other dependencies. Next we have to do the
118 Usually during development only the steps in this second phase have to be
131 it. This means that all source and header files used by the target will have all
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/design_documents/
A Dcmake_framework.rst.txt96 generation or dtc for device tree compilation. These tools have to be found
108 In the provisioning phase, first we have to obtain the necessary resources, i.e.
109 clone the code repository and other dependencies. Next we have to do the
118 Usually during development only the steps in this second phase have to be
131 it. This means that all source and header files used by the target will have all

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