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/trusted-firmware-a/fdts/
A Dstm32mp151.dtsi32 #interrupt-cells = <3>;
33 interrupt-controller;
74 interrupt-parent = <&intc>;
237 interrupt-controller;
238 #interrupt-cells = <3>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
252 interrupt-controller;
519 interrupt-controller;
530 interrupt-controller;
[all …]
A Dfvp-ve-Cortex-A7x1.dts12 interrupt-parent = <&gic>;
32 gic: interrupt-controller@2c001000 {
34 #interrupt-cells = <3>;
36 interrupt-controller;
64 #interrupt-cells = <1>;
65 interrupt-map-mask = <0 0 63>;
66 interrupt-map = <0 0 0 &gic 0 0 4>,
A Dcorstone700.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
34 gic: interrupt-controller@1c000000 {
36 #interrupt-cells = <3>;
38 interrupt-controller;
76 interrupt-parent = <&gic>;
85 interrupt-parent = <&gic>;
120 interrupt-names = "mhu_rx";
132 interrupt-names = "mhu_rx";
144 interrupt-names = "mhu_rx";
A Dn1sdp.dtsi6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
90 gic: interrupt-controller@30000000 {
93 #interrupt-cells = <3>;
96 interrupt-controller;
137 interrupt-names = "eventq", "cmdq-sync", "gerror";
149 interrupt-names = "eventq", "cmdq-sync", "gerror";
167 #interrupt-cells = <1>;
168 interrupt-map-mask = <0 0 0 7>;
190 #interrupt-cells = <1>;
[all …]
A Dmorello.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
20 gic: interrupt-controller@2c010000 {
23 #interrupt-cells = <3>;
26 interrupt-controller;
57 interrupt-names = "mhu_lpri_rx",
A Dfvp-ve-Cortex-A5x1.dts12 interrupt-parent = <&gic>;
52 gic: interrupt-controller@2c001000 {
54 #interrupt-cells = <3>;
56 interrupt-controller;
132 #interrupt-cells = <1>;
133 interrupt-map-mask = <0 0 63>;
134 interrupt-map = <0 0 0 &gic 0 0 4>,
A Dfvp-base-gicv2-psci-aarch32.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
90 gic: interrupt-controller@2f000000 {
92 #interrupt-cells = <3>;
94 interrupt-controller;
149 #interrupt-cells = <1>;
150 interrupt-map-mask = <0 0 63>;
151 interrupt-map = <0 0 0 &gic 0 0 4>,
A Dfvp-base-gicv3-psci-aarch32-common.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
82 gic: interrupt-controller@2f000000 {
84 #interrupt-cells = <3>;
88 interrupt-controller;
150 #interrupt-cells = <1>;
151 interrupt-map-mask = <0 0 63>;
152 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
A Da5ds.dts12 interrupt-parent = <&gic>;
97 gic: interrupt-controller@1c001000 {
99 #interrupt-cells = <3>;
101 interrupt-controller;
110 interrupt-parent = <&gic>;
119 interrupt-parent = <&gic>;
150 interrupt-parent = <&gic>;
A Dfvp-foundation-gicv2-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
90 gic: interrupt-controller@2f000000 {
92 #interrupt-cells = <3>;
94 interrupt-controller;
A Dfvp-foundation-gicv3-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
90 gic: interrupt-controller@2f000000 {
92 #interrupt-cells = <3>;
96 interrupt-controller;
A Darm_fpga.dts11 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
89 gic: interrupt-controller@30000000 {
92 #interrupt-cells = <3>;
95 interrupt-controller;
A Dfvp-base-gicv3-psci-common.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
83 * terminology. Each interrupt property descriptor has 3 fields:
86 * 3. Type of interrupt (Edge or Level configured)
151 gic: interrupt-controller@2f000000 {
153 #interrupt-cells = <3>;
157 interrupt-controller;
A Dfvp-base-gicv2-psci.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
24 interrupt-parent = <&gic>;
89 gic: interrupt-controller@2f000000 {
91 #interrupt-cells = <3>;
93 interrupt-controller;
A Dcorstone700_fpga.dts18 interrupt-parent = <&gic>;
27 interrupt-parent = <&gic>;
A Dn1sdp-multi-chip.dts63 interrupt-names = "eventq", "cmdq-sync", "gerror";
81 #interrupt-cells = <1>;
82 interrupt-map-mask = <0 0 0 7>;
83 interrupt-map = <0 0 0 1 &gic 0 0 0 649 IRQ_TYPE_LEVEL_HIGH>,
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/
A Dplatform-interrupt-controller-API.rst.txt22 is read to determine the priority of the interrupt.
76 interrupt.
136 returns ``1`` for all interrupt types.
142 - For interrupt type ``INTR_TYPE_EL3``:
150 - For interrupt type ``INTR_TYPE_S_EL1``:
179 assign the interrupt to the right group.
183 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
185 - ``INTR_TYPE_S_EL1`` maps to Secure Group 1 interrupt.
187 - ``INTR_TYPE_EL3`` maps to Secure Group 0 interrupt.
191 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
[all …]
A Dexception-handling.rst.txt112 handling concludes by EOIing the interrupt.
171 Dispatchers are assigned interrupt priority levels in two steps:
272 The interrupt handler should have the following signature:
409 deactivating interrupt:
480 #. A Non-secure interrupt preempts Secure execution. Non-secure interrupt is
519 interrupt handler.
540 interrupt, and is taken to EL3.
547 the interrupt received.
556 .. _non-interrupt-flow:
559 interrupt:
[all …]
/trusted-firmware-a/docs/components/
A Dplatform-interrupt-controller-API.rst22 is read to determine the priority of the interrupt.
76 interrupt.
136 returns ``1`` for all interrupt types.
142 - For interrupt type ``INTR_TYPE_EL3``:
150 - For interrupt type ``INTR_TYPE_S_EL1``:
179 assign the interrupt to the right group.
183 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
185 - ``INTR_TYPE_S_EL1`` maps to Secure Group 1 interrupt.
187 - ``INTR_TYPE_EL3`` maps to Secure Group 0 interrupt.
191 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
[all …]
A Dexception-handling.rst112 handling concludes by EOIing the interrupt.
171 Dispatchers are assigned interrupt priority levels in two steps:
272 The interrupt handler should have the following signature:
409 deactivating interrupt:
480 #. A Non-secure interrupt preempts Secure execution. Non-secure interrupt is
519 interrupt handler.
540 interrupt, and is taken to EL3.
547 the interrupt received.
556 .. _non-interrupt-flow:
559 interrupt:
[all …]
A Dsecure-partition-manager.rst906 trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt
910 Non-secure interrupt handling
924 Secure interrupt handling
949 Secure interrupt signaling mechanisms
981 Secure interrupt completion mechanisms
1009 action specified for the same type of interrupt when the SP is in the interrupt
1029 The following figure describes interrupt handling flow when secure interrupt
1042 interrupt id as argument and resume it using ERET.
1047 interrupt and resumes SP vCPU.
1052 The following figure describes interrupt handling flow when secure interrupt
[all …]
/trusted-firmware-a/docs/design/
A Dinterrupt-framework-design.rst35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
39 #. Non-secure interrupt. This type of interrupt can be routed to EL3,
44 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
149 by EL3 interrupt and can handover the interrupt to EL3 for handling.
189 interrupt signal, and if any one of the interrupt type sets **TEL3=1** for a
208 and Secure-EL1 interrupt), only interrupt controller architectures
352 the type of interrupt.
631 When an interrupt is generated, the vector for each interrupt type is
693 #. Validating the interrupt. This involves ensuring that the interrupt was
697 the interrupt was taken from to determine this. If the interrupt is not
[all …]
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/
A Dinterrupt-framework-design.rst.txt35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
39 #. Non-secure interrupt. This type of interrupt can be routed to EL3,
44 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
149 by EL3 interrupt and can handover the interrupt to EL3 for handling.
189 interrupt signal, and if any one of the interrupt type sets **TEL3=1** for a
208 and Secure-EL1 interrupt), only interrupt controller architectures
352 the type of interrupt.
631 When an interrupt is generated, the vector for each interrupt type is
693 #. Validating the interrupt. This involves ensuring that the interrupt was
697 the interrupt was taken from to determine this. If the interrupt is not
[all …]
/trusted-firmware-a/plat/st/stm32mp1/
A Dstm32mp1_pm.c32 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; in stm32_cpu_standby() local
42 while (interrupt == GIC_SPURIOUS_INTERRUPT) { in stm32_cpu_standby()
46 interrupt = gicv2_acknowledge_interrupt(); in stm32_cpu_standby()
48 if ((interrupt != PENDING_G1_INTID) && in stm32_cpu_standby()
49 (interrupt != GIC_SPURIOUS_INTERRUPT)) { in stm32_cpu_standby()
50 gicv2_end_of_interrupt(interrupt); in stm32_cpu_standby()
/trusted-firmware-a/docs/resources/diagrams/plantuml/
A Dsdei_general.puml12 participant "SDEI interrupt source" as SDEI
26 SDEI-->EL3: SDEI interrupt

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