| /trusted-firmware-a/lib/aarch64/ |
| A D | misc_helpers.S | 210 b.lo .Lzeromem_dczva_fallback_entry
289 b.lo 1b
311 b.lo 1b
331 b.lo 1b
399 b.lo m_loop1
533 b.lo 2f
543 b.lo 1b
583 b.lo 2f
594 b.lo 1b
|
| A D | cache_helpers.S | 33 b.lo loop_\op
104 b.lo level_done // nothing to do if no cache or icache
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| /trusted-firmware-a/drivers/coreboot/cbmem_console/aarch64/ |
| A D | cbmem_console.S | 65 b.lo putc_within_bounds
73 b.lo putc_write_back /* ...skip overflow handling */
|
| /trusted-firmware-a/drivers/arm/cci/ |
| A D | cci.c | 17 #define MAKE_CCI_PART_NUMBER(hi, lo) (((hi) << 8) | (lo)) argument
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| A D | ari.c | 81 uint32_t lo, uint32_t hi) in ari_request_wait() argument
88 ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO); in ari_request_wait()
103 ((lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) || in ari_request_wait()
104 (lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) { in ari_request_wait()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | arm-sip-service.rst.txt | 50 uint32_t PC lo
52 uint32_t Cookie lo
60 The parameters *PC hi* and *PC lo* defines upper and lower words, respectively,
65 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
88 and 1 populated with the supplied *Cookie hi* and *Cookie lo* values,
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| /trusted-firmware-a/docs/components/ |
| A D | arm-sip-service.rst | 50 uint32_t PC lo
52 uint32_t Cookie lo
60 The parameters *PC hi* and *PC lo* defines upper and lower words, respectively,
65 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
88 and 1 populated with the supplied *Cookie hi* and *Cookie lo* values,
|
| /trusted-firmware-a/common/aarch64/ |
| A D | debug.S | 126 b.lo 2f
|
| /trusted-firmware-a/include/lib/cpus/aarch64/ |
| A D | cpu_macros.S | 285 ASM_ASSERT(lo)
|
| /trusted-firmware-a/plat/nvidia/tegra/common/aarch64/ |
| A D | tegra_helpers.S | 222 b.lo _loop1
|
| /trusted-firmware-a/build/qemu/release/bl2/ |
| A D | bl2.dump | 2194 e01c98c: 54000263 b.cc e01c9d8 <tf_log+0x7c> // b.lo, b.ul, b.last
3074 e01d5f4: 54ffffa3 b.cc e01d5e8 <loop_civac> // b.lo, b.ul, b.last
3094 e01d62c: 54ffffa3 b.cc e01d620 <loop_cvac> // b.lo, b.ul, b.last
3114 e01d664: 54ffffa3 b.cc e01d658 <loop_ivac> // b.lo, b.ul, b.last
3134 e01d694: 54000523 b.cc e01d738 <zero_normalmem+0xbc> // b.lo, b.ul, b.last
3155 e01d6e8: 54ffffc3 b.cc e01d6e0 <zero_normalmem+0x64> // b.lo, b.ul, b.last
3162 e01d704: 54ffffa3 b.cc e01d6f8 <zero_normalmem+0x7c> // b.lo, b.ul, b.last
4288 e01e724: 1a9f27e0 cset w0, cc // cc = lo, ul, last
4317 e01e790: 54ffffa3 b.cc e01e784 <fdt_splice_+0x4c> // b.lo, b.ul, b.last
4320 e01e79c: 54ffff43 b.cc e01e784 <fdt_splice_+0x4c> // b.lo, b.ul, b.last
[all …]
|
| /trusted-firmware-a/build/qemu/release/bl1/ |
| A D | bl1.dump | 2131 16b0: 54000263 b.cc 16fc <tf_log+0x7c> // b.lo, b.ul, b.last
2760 1fbc: 540008a3 b.cc 20d0 <mmap_add_region_ctx+0x218> // b.lo, b.ul, b.last
3320 273c: 54000043 b.cc 2744 <asm_print_hex_bits+0x1c> // b.lo, b.ul, b.last
3361 27b8: 54ffffa3 b.cc 27ac <loop_civac> // b.lo, b.ul, b.last
3381 27f0: 54ffffa3 b.cc 27e4 <loop_cvac> // b.lo, b.ul, b.last
3398 281c: 54000523 b.cc 28c0 <zero_normalmem+0xbc> // b.lo, b.ul, b.last
3419 2870: 54ffffc3 b.cc 2868 <zero_normalmem+0x64> // b.lo, b.ul, b.last
3426 288c: 54ffffa3 b.cc 2880 <zero_normalmem+0x7c> // b.lo, b.ul, b.last
3432 28a4: 54ffffc3 b.cc 289c <zero_normalmem+0x98> // b.lo, b.ul, b.last
3453 28f0: 540000a3 b.cc 2904 <m_loop1> // b.lo, b.ul, b.last
[all …]
|
| /trusted-firmware-a/build/qemu/release/bl31/ |
| A D | bl31.dump | 1075 e040480: 54ffffa3 b.cc e040474 <loop_cvac> // b.lo, b.ul, b.last
1436 e0408cc: 540001e3 b.cc e040908 <level_done> // b.lo, b.ul, b.last
1755 e040d20: 54ffffa3 b.cc e040d14 <loop_civac> // b.lo, b.ul, b.last
1812 e040dcc: 54ffffa3 b.cc e040dc0 <loop_ivac> // b.lo, b.ul, b.last
2129 e041198: 54000523 b.cc e04123c <zero_normalmem+0xbc> // b.lo, b.ul, b.last
2150 e0411ec: 54ffffc3 b.cc e0411e4 <zero_normalmem+0x64> // b.lo, b.ul, b.last
3602 e04263c: 54000043 b.cc e042644 <memmove+0x14> // b.lo, b.ul, b.last
5096 e043be4: 9a9f3041 csel x1, x2, xzr, cc // cc = lo, ul, last
5554 e044274: 54000d43 b.cc e04441c <psci_setup+0x21c> // b.lo, b.ul, b.last
5572 e0442bc: 54001083 b.cc e0444cc <psci_setup+0x2cc> // b.lo, b.ul, b.last
[all …]
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| /trusted-firmware-a/docs/build/TF-A_2.5/ |
| A D | searchindex.js | 1 …c_enabl:86,llc_sram:[6,86],lld:[6,52],llvm:[2,6,52,60,131],lm:4,ln:[78,79],lo:[8,54],load:[2,6,13,…
|
| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.tex | 13559 \PYG{n}{uint32\PYGZus{}t} \PYG{n}{PC} \PYG{n}{lo}
13561 \PYG{n}{uint32\PYGZus{}t} \PYG{n}{Cookie} \PYG{n}{lo}
13572 The parameters \sphinxstyleemphasis{PC hi} and \sphinxstyleemphasis{PC lo} defines upper and lower …
13578 switched, the parameters \sphinxstyleemphasis{Cookie hi} and \sphinxstyleemphasis{Cookie lo} are pa…
13612 …lated with the supplied \sphinxstyleemphasis{Cookie hi} and \sphinxstyleemphasis{Cookie lo} values,
|