| /trusted-firmware-a/plat/marvell/armada/a8k/common/ble/ |
| A D | ble_main.c | 25 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in mailbox_clean() local
27 memset(mailbox, 0, PLAT_MARVELL_MAILBOX_SIZE); in mailbox_clean()
33 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in exec_ble_main() local
64 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || in exec_ble_main()
65 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) { in exec_ble_main()
70 (void (*)(void))mailbox[MBOX_IDX_ROM_EXIT_ADDR]; in exec_ble_main()
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| /trusted-firmware-a/plat/marvell/armada/common/ |
| A D | marvell_pm.c | 26 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in marvell_program_mailbox() local
33 ((PLAT_MARVELL_MAILBOX_BASE + sizeof(*mailbox)) <= in marvell_program_mailbox()
36 mailbox[MBOX_IDX_MAGIC] = MVEBU_MAILBOX_MAGIC_NUM; in marvell_program_mailbox()
37 mailbox[MBOX_IDX_SEC_ADDR] = address; in marvell_program_mailbox()
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| /trusted-firmware-a/plat/marvell/armada/a8k/common/ |
| A D | plat_bl31_setup.c | 106 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in bl31_plat_arch_setup() local
119 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || in bl31_plat_arch_setup()
120 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) in bl31_plat_arch_setup()
140 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || in bl31_plat_arch_setup()
141 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) in bl31_plat_arch_setup()
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| A D | plat_pm.c | 623 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in a8k_pwr_domain_suspend() local
632 mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; in a8k_pwr_domain_suspend()
633 mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_marvell_exit_bootrom; in a8k_pwr_domain_suspend()
695 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in a8k_pwr_domain_suspend_finish() local
710 mailbox[MBOX_IDX_SUSPEND_MAGIC] = 0; in a8k_pwr_domain_suspend_finish()
711 mailbox[MBOX_IDX_ROM_EXIT_ADDR] = 0; in a8k_pwr_domain_suspend_finish()
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| /trusted-firmware-a/plat/hisilicon/hikey960/drivers/ipc/ |
| A D | hisi_ipc.c | 139 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_on_off() local
144 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_pm_on_off()
153 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_suspend() local
162 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_pm_suspend()
170 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_off() local
175 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_psci_system_off()
184 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_reset() local
189 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_psci_system_reset()
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| /trusted-firmware-a/plat/arm/common/ |
| A D | arm_pm.c | 185 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; in plat_arm_program_trusted_mailbox() local
187 *mailbox = address; in plat_arm_program_trusted_mailbox()
194 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ in plat_arm_program_trusted_mailbox()
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| /trusted-firmware-a/plat/arm/board/a5ds/ |
| A D | a5ds_pm.c | 69 uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE; in plat_setup_psci_ops() local
70 *mailbox = sec_entrypoint; in plat_setup_psci_ops()
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| /trusted-firmware-a/plat/qemu/qemu_sbsa/ |
| A D | sbsa_pm.c | 230 uintptr_t *mailbox = (uintptr_t *)PLAT_QEMU_TRUSTED_MAILBOX_BASE; in plat_setup_psci_ops() local
232 *mailbox = sec_entrypoint; in plat_setup_psci_ops()
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| /trusted-firmware-a/plat/qemu/common/ |
| A D | qemu_pm.c | 250 uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; in plat_setup_psci_ops() local
252 *mailbox = sec_entrypoint; in plat_setup_psci_ops()
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| /trusted-firmware-a/fdts/ |
| A D | morello-fvp.dts | 146 mboxes = <&mailbox 1 0 &mailbox 1 1>;
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| A D | morello.dtsi | 52 mailbox: mhu@45000000 { label
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| /trusted-firmware-a/plat/renesas/common/include/ |
| A D | rcar_private.h | 16 typedef volatile struct mailbox { struct
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/fvp/ |
| A D | index.rst.txt | 174 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
178 clear the mailbox at start-up.
185 dd if=/dev/zero of=mailbox.dat bs=1 count=8
187 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
192 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
193 --data=mailbox.dat@0x04000000 [Foundation FVP]
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| /trusted-firmware-a/docs/plat/arm/fvp/ |
| A D | index.rst | 174 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
178 clear the mailbox at start-up.
185 dd if=/dev/zero of=mailbox.dat bs=1 count=8
187 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
192 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
193 --data=mailbox.dat@0x04000000 [Foundation FVP]
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| /trusted-firmware-a/plat/rpi/rpi3/ |
| A D | platform.mk | 29 drivers/rpi3/mailbox/rpi3_mbox.c \
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| /trusted-firmware-a/docs/plat/ |
| A D | stm32mp1.rst | 79 | SCMI mailbox | |
|
| A D | rpi3.rst | 172 kernel. This mailbox is located at a different address in the AArch32 default
185 address to the mailbox so that the secondary CPUs jump to it and are recognised
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | stm32mp1.rst.txt | 79 | SCMI mailbox | |
|
| A D | rpi3.rst.txt | 172 kernel. This mailbox is located at a different address in the AArch32 default
185 address to the mailbox so that the secondary CPUs jump to it and are recognised
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| /trusted-firmware-a/docs/plat/marvell/armada/ |
| A D | build.rst | 194 TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/ |
| A D | build.rst.txt | 194 TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
|
| /trusted-firmware-a/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 196 and is used to configure the platform mailbox. Helper macros are provided in
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | psci-lib-integration-guide.rst.txt | 196 and is used to configure the platform mailbox. Helper macros are provided in
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | change-log.md.txt | 2078 - intel: Introduce mailbox response length handling
2120 - xilinx: versal: Enable ipi mailbox service
2204 - intel: Modify non secure access function, BL31 address mapping, mailbox's
2252 - xilinx: Move ipi mailbox svc to xilinx common
2310 mailbox config return status, mailbox driver logic, FPGA manager on
2311 reconfiguration, and mailbox send_cmd issue
|
| /trusted-firmware-a/docs/ |
| A D | change-log.md | 2078 - intel: Introduce mailbox response length handling
2120 - xilinx: versal: Enable ipi mailbox service
2204 - intel: Modify non secure access function, BL31 address mapping, mailbox's
2252 - xilinx: Move ipi mailbox svc to xilinx common
2310 mailbox config return status, mailbox driver logic, FPGA manager on
2311 reconfiguration, and mailbox send_cmd issue
|