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Searched refs:mask (Results 1 – 25 of 114) sorted by relevance

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/trusted-firmware-a/drivers/marvell/comphy/
A Dphy-comphy-cp110.c125 reg &= ~mask; in mvebu_cp110_comphy_clr_pipe_selector()
149 reg &= ~mask; in mvebu_cp110_comphy_clr_phy_selector()
176 reg &= ~mask; in mvebu_cp110_comphy_set_phy_selector()
265 reg &= ~mask; in mvebu_cp110_comphy_set_pipe_selector()
316 mask = data; in mvebu_cp110_comphy_is_pll_locked()
817 mask = data; in mvebu_cp110_comphy_sgmii_power_on()
1209 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1229 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1433 mask = 0; in mvebu_cp110_comphy_pcie_power_on()
1896 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
[all …]
A Dphy-comphy-3700.c374 uint32_t mask, data; in mvebu_a3700_comphy_sgmii_power_on() local
408 reg_set(offset, data, mask); in mvebu_a3700_comphy_sgmii_power_on()
444 mask = PHY_MODE_MASK; in mvebu_a3700_comphy_sgmii_power_on()
452 mask = PHY_REF_CLK_SEL; in mvebu_a3700_comphy_sgmii_power_on()
464 mask = REF_FREF_SEL_MASK; in mvebu_a3700_comphy_sgmii_power_on()
479 mask = SEL_DATA_WIDTH_MASK; in mvebu_a3700_comphy_sgmii_power_on()
595 uint32_t mask, data; in mvebu_a3700_comphy_sgmii_power_off() local
600 mask = data; in mvebu_a3700_comphy_sgmii_power_off()
617 uint16_t mask); in mvebu_a3700_comphy_usb3_power_on()
649 mask); in mvebu_a3700_comphy_usb3_power_on()
[all …]
A Dphy-comphy-common.h125 uint32_t mask, in polling_with_timeout() argument
134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() argument
148 addr, data, mask); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data); in reg_set()
156 uint16_t mask) in reg_set16() argument
160 addr, data, mask); in reg_set16()
162 mmio_clrsetbits_16(addr, mask, data); in reg_set16()
/trusted-firmware-a/plat/mediatek/common/
A Dmtk_cirq.c38 mask->mask1); in mt_irq_mask_restore()
40 mask->mask2); in mt_irq_mask_restore()
42 mask->mask3); in mt_irq_mask_restore()
44 mask->mask4); in mt_irq_mask_restore()
46 mask->mask5); in mt_irq_mask_restore()
48 mask->mask6); in mt_irq_mask_restore()
50 mask->mask7); in mt_irq_mask_restore()
52 mask->mask8); in mt_irq_mask_restore()
54 mask->mask9); in mt_irq_mask_restore()
56 mask->mask10); in mt_irq_mask_restore()
[all …]
/trusted-firmware-a/services/std_svc/trng/
A Dtrng_main.c25 uint32_t mask = ~0U; in trng_rnd32() local
37 mask >>= 32U - (nbits % 32U); in trng_rnd32()
42 SMC_RET4(handle, TRNG_E_SUCCESS, 0, 0, ent[0] & mask); in trng_rnd32()
45 SMC_RET4(handle, TRNG_E_SUCCESS, 0, (ent[0] >> 32) & mask, in trng_rnd32()
49 SMC_RET4(handle, TRNG_E_SUCCESS, ent[1] & mask, in trng_rnd32()
61 uint64_t mask = ~0ULL; in trng_rnd64() local
74 mask >>= 64U - (nbits % 64U); in trng_rnd64()
79 SMC_RET4(handle, TRNG_E_SUCCESS, 0, 0, ent[0] & mask); in trng_rnd64()
82 SMC_RET4(handle, TRNG_E_SUCCESS, 0, ent[1] & mask, ent[0]); in trng_rnd64()
85 SMC_RET4(handle, TRNG_E_SUCCESS, ent[2] & mask, ent[1], ent[0]); in trng_rnd64()
/trusted-firmware-a/plat/xilinx/zynqmp/pm_service/
A Dpm_api_ioctl.c178 unsigned int val, mask, shift; in pm_ioctl_set_sgmii_mode() local
234 unsigned int mask, val; in pm_ioctl_sd_dll_reset() local
238 mask = ZYNQMP_SD0_DLL_RST_MASK; in pm_ioctl_sd_dll_reset()
241 mask = ZYNQMP_SD1_DLL_RST_MASK; in pm_ioctl_sd_dll_reset()
285 unsigned int val, mask; in pm_ioctl_sd_set_tapdelay() local
289 mask = ZYNQMP_SD0_DLL_RST_MASK; in pm_ioctl_sd_set_tapdelay()
302 if ((val & mask) == 0) { in pm_ioctl_sd_set_tapdelay()
346 if ((val & mask) == 0) { in pm_ioctl_sd_set_tapdelay()
505 unsigned int mask; in pm_ioctl_afi() local
528 mask = FABRIC_WIDTH; in pm_ioctl_afi()
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/trusted-firmware-a/plat/nvidia/tegra/soc/t210/
A Dplat_psci_handlers.c275 uint32_t val, mask; in tegra_reset_all_dma_masters() local
307 mask = GPU_RESET_BIT; in tegra_reset_all_dma_masters()
308 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
311 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | in tegra_reset_all_dma_masters()
314 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
321 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
326 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
332 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
336 mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; in tegra_reset_all_dma_masters()
337 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
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/trusted-firmware-a/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc.c127 int spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
129 return mmio_read_32(SPM_PWR_STATUS) & mask; in spm_get_powerstate()
134 uint32_t mask; in spm_get_cluster_powerstate() local
138 return spm_get_powerstate(mask); in spm_get_cluster_powerstate()
259 uint32_t mask; in spm_poweroff_cluster() local
266 mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK : in spm_poweroff_cluster()
268 mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask); in spm_poweroff_cluster()
270 while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask) in spm_poweroff_cluster()
279 mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask); in spm_poweroff_cluster()
313 uint32_t mask; in spm_poweron_cluster() local
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/trusted-firmware-a/lib/cpus/aarch64/
A Dcpuamu.c15 unsigned int mask; member
38 ctx->mask = cpuamu_read_cpuamcntenset_el0(); in cpuamu_context_save()
41 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_save()
60 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_restore()
69 cpuamu_write_cpuamcntenset_el0(ctx->mask); in cpuamu_context_restore()
/trusted-firmware-a/drivers/arm/smmu/
A Dsmmu_v3.c16 static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, in smmuv3_poll() argument
26 if ((reg_val & mask) == value) in smmuv3_poll()
32 value == 0U ? reg_val & ~mask : reg_val | mask); in smmuv3_poll()
/trusted-firmware-a/drivers/nxp/sfp/
A Dfuse_prov.c24 uint32_t mask) in write_a_fuse() argument
29 if ((last_stored_val & mask) == mask) { in write_a_fuse()
34 sfp_write32(fuse_addr, last_stored_val | (*fuse_hdr_val & mask)); in write_a_fuse()
37 if (sfp_read32(fuse_addr) != (last_stored_val | (*fuse_hdr_val & mask))) { in write_a_fuse()
329 uint32_t mask = 0; in prog_ospr1() local
333 mask = OSPR1_MC_MASK; in prog_ospr1()
337 mask = mask | OSPR1_DBG_LVL_MASK; in prog_ospr1()
340 ret = write_a_fuse(&sfp_ccsr_regs->ospr1, &fuse_hdr->ospr1, mask); in prog_ospr1()
/trusted-firmware-a/drivers/st/pmic/
A Dstpmic1.c625 uint8_t mask; in stpmic1_regulator_voltage_set() local
629 mask = BUCK_VOLTAGE_MASK; in stpmic1_regulator_voltage_set()
632 mask = LDO_VOLTAGE_MASK; in stpmic1_regulator_voltage_set()
639 mask); in stpmic1_regulator_voltage_set()
670 uint8_t mask; in stpmic1_regulator_voltage_get() local
675 mask = BUCK_VOLTAGE_MASK; in stpmic1_regulator_voltage_get()
678 mask = LDO_VOLTAGE_MASK; in stpmic1_regulator_voltage_get()
688 value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT; in stpmic1_regulator_voltage_get()
736 int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask) in stpmic1_register_update() argument
746 val = (val & ~mask) | (value & mask); in stpmic1_register_update()
/trusted-firmware-a/plat/mediatek/mt8183/drivers/mcdi/
A Dmtk_mcdi.h18 uint32_t mcdi_avail_cpu_mask_write(uint32_t mask);
19 uint32_t mcdi_avail_cpu_mask_set(uint32_t mask);
20 uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask);
A Dmtk_mcdi.c48 uint32_t mcdi_avail_cpu_mask_write(uint32_t mask) in mcdi_avail_cpu_mask_write() argument
50 mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask); in mcdi_avail_cpu_mask_write()
52 return mask; in mcdi_avail_cpu_mask_write()
55 uint32_t mcdi_avail_cpu_mask_set(uint32_t mask) in mcdi_avail_cpu_mask_set() argument
60 m |= mask; in mcdi_avail_cpu_mask_set()
66 uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask) in mcdi_avail_cpu_mask_clr() argument
71 m &= ~mask; in mcdi_avail_cpu_mask_clr()
/trusted-firmware-a/plat/imx/common/sci/
A Dimx8_mu.c46 uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; in MU_SendMessage() local
49 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) in MU_SendMessage()
56 uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; in MU_ReceiveMsg() local
59 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) in MU_ReceiveMsg()
/trusted-firmware-a/plat/allwinner/common/
A Darisc_off.S19 # It expects the core number presented as a mask in the upper half of
26 # - Using that mask, activate the core output clamps by setting the
30 # - Using the negated mask, assert the core's reset line by clearing the
65 l.xori r6, r6, -1 # negate core mask
69 l.ff1 r6, r3 # get core number from high mask
83 l.movhi r3, 0 # FIXUP! with core mask
88 l.and r5, r5, r3 # mask requested core
92 l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
/trusted-firmware-a/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc.c66 bool spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
68 return (mmio_read_32(MCUCFG_CPC_SPMC_PWR_STATUS) & mask) != 0U; in spm_get_powerstate()
80 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate() local
84 return spm_get_powerstate(mask); in spm_get_cpu_powerstate()
/trusted-firmware-a/plat/hisilicon/hikey960/
A Dhikey960_bl1_setup.c111 unsigned int data, mask; in hikey960_ufs_reset() local
136 mask = SC_DIV_UFS_PERIBUS << 16; in hikey960_ufs_reset()
137 mmio_write_32(CRG_CLKDIV17_REG, mask); in hikey960_ufs_reset()
139 mask = SC_DIV_UFSPHY_CFG_MASK << 16; in hikey960_ufs_reset()
141 mmio_write_32(CRG_CLKDIV16_REG, mask | data); in hikey960_ufs_reset()
A Dhikey960_bl2_setup.c86 unsigned int data, mask; in hikey960_ufs_reset() local
111 mask = SC_DIV_UFS_PERIBUS << 16; in hikey960_ufs_reset()
112 mmio_write_32(CRG_CLKDIV17_REG, mask); in hikey960_ufs_reset()
114 mask = SC_DIV_UFSPHY_CFG_MASK << 16; in hikey960_ufs_reset()
116 mmio_write_32(CRG_CLKDIV16_REG, mask | data); in hikey960_ufs_reset()
/trusted-firmware-a/plat/socionext/uniphier/
A Duniphier_soc_info.c15 static unsigned int uniphier_get_revision_field(unsigned int mask, in uniphier_get_revision_field() argument
25 return (mmio_read_32(reg) >> shift) & mask; in uniphier_get_revision_field()
/trusted-firmware-a/include/lib/cpus/aarch64/
A Dcortex_a75.h51 void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
52 void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
A Dcpuamu.h39 void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
40 void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
/trusted-firmware-a/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc.c66 bool spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
68 return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask) != 0U; in spm_get_powerstate()
80 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate() local
84 return spm_get_powerstate(mask); in spm_get_cpu_powerstate()
/trusted-firmware-a/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_cond.c77 #define IDLE_CG(mask, addr, bitflip, clkmux) \ argument
78 {mask, (uintptr_t)addr, bitflip, clkmux}
154 #define IS_MT_SPM_PWR_OFF(mask) \ argument
155 (((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
156 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
/trusted-firmware-a/plat/hisilicon/hikey960/drivers/pwrc/
A Dhisi_pwrc.c270 unsigned int mask = 0xF; in check_hotplug() local
273 ((boot_flag & mask) == mask)) in check_hotplug()
281 unsigned int mask = 0xf << (core * 4); in hisi_test_pwrdn_allcores() local
286 mask = (PDC_COREPWRSTAT_MASK & (~mask)); in hisi_test_pwrdn_allcores()
287 pdc_stat &= mask; in hisi_test_pwrdn_allcores()

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