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Searched refs:meminfo_t (Results 1 – 25 of 45) sorted by relevance

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/trusted-firmware-a/plat/common/
A Dplat_bl1_common.c83 meminfo_t *bl2_secram_layout; in bl1_plat_handle_post_image_load()
84 meminfo_t *bl1_secram_layout; in bl1_plat_handle_post_image_load()
108 bl2_secram_layout = (meminfo_t *) bl1_secram_layout->total_base; in bl1_plat_handle_post_image_load()
/trusted-firmware-a/plat/arm/board/fvp_r/
A Dfvp_r_bl1_setup.c52 static meminfo_t bl1_tzram_layout;
213 meminfo_t *bl33_secram_layout; in bl1_plat_handle_post_image_load()
214 meminfo_t *bl1_secram_layout; in bl1_plat_handle_post_image_load()
238 bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base; in bl1_plat_handle_post_image_load()
A Dfvp_r_bl1_main.c98 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, in bl1_calc_bl2_mem_layout()
99 meminfo_t *bl2_mem_layout) in bl1_calc_bl2_mem_layout()
112 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); in bl1_calc_bl2_mem_layout()
/trusted-firmware-a/plat/hisilicon/poplar/
A Dbl1_plat_setup.c29 static meminfo_t bl1_tzram_layout;
30 static meminfo_t bl2_tzram_layout;
59 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); in bl1_plat_handle_post_image_load()
/trusted-firmware-a/plat/rpi/rpi3/
A Drpi3_bl2_setup.c25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
51 meminfo_t *mem_layout = (meminfo_t *) arg1; in bl2_early_platform_setup2()
A Drpi3_bl1_setup.c20 static meminfo_t bl1_tzram_layout;
22 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/trusted-firmware-a/plat/marvell/armada/common/
A Dmarvell_bl2_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
35 meminfo_t *bl2_plat_sec_mem_layout(void) in bl2_plat_sec_mem_layout()
46 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) in marvell_bl2_early_platform_setup()
A Dmarvell_bl1_setup.c26 static meminfo_t bl1_ram_layout;
28 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/trusted-firmware-a/plat/qemu/common/
A Dqemu_bl1_setup.c18 static meminfo_t bl1_tzram_layout;
21 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
A Dqemu_bl2_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
32 meminfo_t *mem_layout = (void *)arg1; in bl2_early_platform_setup2()
/trusted-firmware-a/plat/layerscape/common/
A Dls_bl1_setup.c14 static meminfo_t bl1_tzram_layout;
16 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
A Dls_bl2_setup.c17 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
24 void ls_bl2_early_platform_setup(meminfo_t *mem_layout) in ls_bl2_early_platform_setup()
/trusted-firmware-a/plat/brcm/common/
A Dbrcm_bl2_setup.c22 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
48 meminfo_t *mem_layout) in bcm_bl2_early_platform_setup()
75 bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/trusted-firmware-a/include/bl1/
A Dbl1.h98 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
99 meminfo_t *bl2_mem_layout);
/trusted-firmware-a/bl1/
A Dbl1_main.c37 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, in bl1_calc_bl2_mem_layout()
38 meminfo_t *bl2_mem_layout) in bl1_calc_bl2_mem_layout()
51 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); in bl1_calc_bl2_mem_layout()
/trusted-firmware-a/plat/hisilicon/hikey/
A Dhikey_bl1_setup.c30 static meminfo_t bl1_tzram_layout;
40 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
/trusted-firmware-a/plat/layerscape/board/ls1043/
A Dls1043_bl2_setup.c15 ls_bl2_early_platform_setup((meminfo_t *)arg1); in bl2_early_platform_setup2()
/trusted-firmware-a/plat/arm/board/a5ds/
A Da5ds_bl2_setup.c12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/trusted-firmware-a/plat/arm/board/fvp_ve/
A Dfvp_ve_bl2_setup.c18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/trusted-firmware-a/plat/arm/css/common/
A Dcss_bl2u_setup.c25 void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) in bl2u_early_platform_setup()
A Dcss_bl2_setup.c59 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/trusted-firmware-a/plat/arm/common/
A Darm_bl2_setup.c35 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
94 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
A Darm_bl2_el3_setup.c23 static meminfo_t bl2_el3_tzram_layout;
/trusted-firmware-a/plat/layerscape/common/include/
A Dplat_ls.h19 void ls_bl2_early_platform_setup(meminfo_t *mem_layout);
/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_bl2_setup.c23 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()

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