| /trusted-firmware-a/plat/socionext/synquacer/ |
| A D | sq_xlat_setup.c | 20 mmap_add_region(total_base, total_base, in sq_mmap_setup()
27 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, in sq_mmap_setup()
34 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, in sq_mmap_setup()
42 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in sq_mmap_setup()
47 mmap_add_region(SQ_REG_REGION_BASE, SQ_REG_REGION_BASE, in sq_mmap_setup()
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| /trusted-firmware-a/plat/socionext/uniphier/ |
| A D | uniphier_xlat_setup.c | 41 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, in uniphier_mmap_setup()
48 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, in uniphier_mmap_setup()
55 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in uniphier_mmap_setup()
61 mmap_add_region(uniphier_reg_region[soc].base, in uniphier_mmap_setup()
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| /trusted-firmware-a/plat/marvell/armada/common/aarch64/ |
| A D | marvell_common.c | 52 mmap_add_region(total_base, total_base, in marvell_setup_page_tables()
59 mmap_add_region(code_start, code_start, in marvell_setup_page_tables()
66 mmap_add_region(rodata_start, rodata_start, in marvell_setup_page_tables()
74 mmap_add_region(coh_start, coh_start, in marvell_setup_page_tables()
|
| /trusted-firmware-a/plat/rockchip/common/aarch32/ |
| A D | platform_common.c | 26 mmap_add_region(total_base, total_base, total_size, in plat_configure_mmu_svc_mon()
28 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, in plat_configure_mmu_svc_mon()
30 mmap_add_region(coh_start, coh_start, coh_limit - coh_start, in plat_configure_mmu_svc_mon()
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| /trusted-firmware-a/plat/allwinner/common/ |
| A D | sunxi_common.c | 34 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, in sunxi_configure_mmu_el3()
37 mmap_add_region(BL_CODE_END, BL_CODE_END, in sunxi_configure_mmu_el3()
41 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, in sunxi_configure_mmu_el3()
46 mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE, in sunxi_configure_mmu_el3()
51 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in sunxi_configure_mmu_el3()
|
| /trusted-firmware-a/plat/rockchip/common/aarch64/ |
| A D | platform_common.c | 39 mmap_add_region(total_base, total_base, \
42 mmap_add_region(ro_start, ro_start, \
45 mmap_add_region(coh_start, coh_start, \
|
| /trusted-firmware-a/plat/layerscape/common/ |
| A D | ls_common.c | 91 mmap_add_region(total_base, total_base, in ls_setup_page_tables()
98 mmap_add_region(code_start, code_start, in ls_setup_page_tables()
105 mmap_add_region(rodata_start, rodata_start, in ls_setup_page_tables()
113 mmap_add_region(coh_start, coh_start, in ls_setup_page_tables()
|
| /trusted-firmware-a/plat/hisilicon/poplar/aarch64/ |
| A D | platform_common.c | 58 mmap_add_region(total_base, total_base, \
61 mmap_add_region(ro_start, ro_start, \
64 mmap_add_region(coh_start, coh_start, \
|
| /trusted-firmware-a/plat/mediatek/mt8173/aarch64/ |
| A D | platform_common.c | 48 mmap_add_region(total_base, total_base, \
51 mmap_add_region(ro_start, ro_start, \
54 mmap_add_region(coh_start, coh_start, \
|
| /trusted-firmware-a/plat/qemu/common/ |
| A D | qemu_common.c | 137 mmap_add_region(total_base, total_base, \
140 mmap_add_region(code_start, code_start, \
143 mmap_add_region(ro_start, ro_start, \
146 mmap_add_region(coh_start, coh_start, \
|
| /trusted-firmware-a/plat/nxp/common/setup/ |
| A D | ls_common.c | 71 mmap_add_region(info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
87 mmap_add_region((info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
104 mmap_add_region(info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
195 mmap_add_region(total_base, total_base, in ls_setup_page_tables()
202 mmap_add_region(code_start, code_start, in ls_setup_page_tables()
209 mmap_add_region(rodata_start, rodata_start, in ls_setup_page_tables()
217 mmap_add_region(coh_start, coh_start, in ls_setup_page_tables()
|
| /trusted-firmware-a/plat/mediatek/mt8183/aarch64/ |
| A D | platform_common.c | 45 mmap_add_region(total_base, total_base, total_size, in plat_configure_mmu_el3()
47 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, in plat_configure_mmu_el3()
49 mmap_add_region(coh_start, coh_start, coh_limit - coh_start, in plat_configure_mmu_el3()
|
| /trusted-firmware-a/plat/qti/common/src/ |
| A D | qti_common.c | 94 mmap_add_region(total_base, total_base, in qti_setup_page_tables()
100 mmap_add_region(code_start, code_start, in qti_setup_page_tables()
106 mmap_add_region(rodata_start, rodata_start, in qti_setup_page_tables()
112 mmap_add_region(coh_start, coh_start, in qti_setup_page_tables()
|
| /trusted-firmware-a/plat/hisilicon/hikey/aarch64/ |
| A D | hikey_common.c | 101 mmap_add_region(total_base, total_base, \
104 mmap_add_region(ro_start, ro_start, \
107 mmap_add_region(coh_start, coh_start, \
|
| /trusted-firmware-a/plat/hisilicon/hikey960/aarch64/ |
| A D | hikey960_common.c | 97 mmap_add_region(total_base, total_base, \
100 mmap_add_region(ro_start, ro_start, \
103 mmap_add_region(coh_start, coh_start, \
|
| /trusted-firmware-a/plat/rpi/common/ |
| A D | rpi3_common.c | 165 mmap_add_region(total_base, total_base, in rpi3_setup_page_tables()
172 mmap_add_region(code_start, code_start, in rpi3_setup_page_tables()
179 mmap_add_region(rodata_start, rodata_start, in rpi3_setup_page_tables()
187 mmap_add_region(coh_start, coh_start, in rpi3_setup_page_tables()
|
| /trusted-firmware-a/plat/renesas/common/aarch64/ |
| A D | platform_common.c | 154 mmap_add_region(total_base, total_base, total_size, in rcar_configure_mmu_el3()
156 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, in rcar_configure_mmu_el3()
158 mmap_add_region(coh_start, coh_start, coh_limit - coh_start, in rcar_configure_mmu_el3()
171 mmap_add_region(total_base, total_base, total_size, in rcar_configure_mmu_el3()
173 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, in rcar_configure_mmu_el3()
|
| /trusted-firmware-a/plat/mediatek/mt8195/aarch64/ |
| A D | platform_common.c | 36 mmap_add_region(total_base, total_base, total_size, in plat_configure_mmu_el3()
38 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, in plat_configure_mmu_el3()
|
| /trusted-firmware-a/plat/imx/imx8m/imx8mm/ |
| A D | imx8mm_bl31_setup.c | 144 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), in bl31_plat_arch_setup()
146 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), in bl31_plat_arch_setup()
149 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in bl31_plat_arch_setup()
|
| /trusted-firmware-a/plat/imx/imx8m/imx8mn/ |
| A D | imx8mn_bl31_setup.c | 144 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), in bl31_plat_arch_setup()
146 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), in bl31_plat_arch_setup()
149 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in bl31_plat_arch_setup()
|
| /trusted-firmware-a/plat/imx/imx8m/imx8mp/ |
| A D | imx8mp_bl31_setup.c | 142 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), in bl31_plat_arch_setup()
144 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), in bl31_plat_arch_setup()
147 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in bl31_plat_arch_setup()
|
| /trusted-firmware-a/plat/nvidia/tegra/common/ |
| A D | tegra_bl31_setup.c | 297 mmap_add_region(rw_start, rw_start, in bl31_plat_arch_setup()
300 mmap_add_region(rodata_start, rodata_start, in bl31_plat_arch_setup()
303 mmap_add_region(code_base, code_base, in bl31_plat_arch_setup()
309 mmap_add_region(params_from_bl2->tzdram_base, in bl31_plat_arch_setup()
|
| /trusted-firmware-a/plat/mediatek/mt8192/aarch64/ |
| A D | platform_common.c | 44 mmap_add_region(total_base, total_base, total_size, in plat_configure_mmu_el3()
46 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, in plat_configure_mmu_el3()
|
| /trusted-firmware-a/plat/imx/imx8m/imx8mq/ |
| A D | imx8mq_bl31_setup.c | 166 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), in bl31_plat_arch_setup()
168 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), in bl31_plat_arch_setup()
174 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, in bl31_plat_arch_setup()
|
| /trusted-firmware-a/plat/mediatek/mt6795/ |
| A D | bl31_plat_setup.c | 81 mmap_add_region(total_base, total_base, \
84 mmap_add_region(ro_start, ro_start, \
87 mmap_add_region(coh_start, coh_start, \
267 mmap_add_region( in bl31_plat_arch_setup()
|