/trusted-firmware-a/drivers/renesas/common/ddr/ddr_a/ |
A D | ddr_init_d3.c | 29 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr_d3_1866() 32 mmio_write_32(DBSC_DBTR0, 0x0000000D); in init_ddr_d3_1866() 33 mmio_write_32(DBSC_DBTR1, 0x00000009); in init_ddr_d3_1866() 34 mmio_write_32(DBSC_DBTR2, 0x00000000); in init_ddr_d3_1866() 35 mmio_write_32(DBSC_DBTR3, 0x0000000D); in init_ddr_d3_1866() 108 mmio_write_32(DBSC_DBPDRGD_0, in init_ddr_d3_1866() 311 mmio_write_32(DBSC_DBCALCNF, in init_ddr_d3_1866() 313 mmio_write_32(DBSC_DBRFCNF1, in init_ddr_d3_1866() 456 mmio_write_32(DBSC_DBPDRGD_0, in init_ddr_d3_1600() 657 mmio_write_32(DBSC_DBCALCNF, in init_ddr_d3_1600() [all …]
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A D | ddr_init_e3.c | 92 mmio_write_32(DBSC_DBPHYCONF0, 0x1); in init_ddr() 96 mmio_write_32(DBSC_DBTR0, 0xB); in init_ddr() 97 mmio_write_32(DBSC_DBTR1, 0x8); in init_ddr() 99 mmio_write_32(DBSC_DBTR0, 0xD); in init_ddr() 100 mmio_write_32(DBSC_DBTR1, 0x9); in init_ddr() 664 mmio_write_32(DBSC_DBPDRGD_0, in init_ddr() 747 mmio_write_32(DBSC_DBRFCNF1, in init_ddr() 750 mmio_write_32(DBSC_DBRFCNF1, in init_ddr() 1218 mmio_write_32(DBSC_DBRFCNF1, in recovery_from_backup_mode() 1221 mmio_write_32(DBSC_DBRFCNF1, in recovery_from_backup_mode() [all …]
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A D | ddr_init_v3m.c | 20 mmio_write_32(DBSC_DBKIND, 0x00000007); in init_ddr_v3m_1600() 27 mmio_write_32(DBSC_DBTR0, 0x0000000B); in init_ddr_v3m_1600() 28 mmio_write_32(DBSC_DBTR1, 0x00000008); in init_ddr_v3m_1600() 29 mmio_write_32(DBSC_DBTR3, 0x0000000B); in init_ddr_v3m_1600() 30 mmio_write_32(DBSC_DBTR4, 0x000B000B); in init_ddr_v3m_1600() 31 mmio_write_32(DBSC_DBTR5, 0x00000027); in init_ddr_v3m_1600() 32 mmio_write_32(DBSC_DBTR6, 0x0000001C); in init_ddr_v3m_1600() 33 mmio_write_32(DBSC_DBTR7, 0x00060006); in init_ddr_v3m_1600() 34 mmio_write_32(DBSC_DBTR8, 0x00000020); in init_ddr_v3m_1600() 35 mmio_write_32(DBSC_DBTR9, 0x00000006); in init_ddr_v3m_1600() [all …]
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/trusted-firmware-a/plat/nxp/common/soc_errata/ |
A D | errata_a050426.c | 16 mmio_write_32(0x700117E60, (val3 | 0x80000001)); in erratum_a050426() 18 mmio_write_32(0x700117E90, (val4 & 0xFFDFFFFF)); in erratum_a050426() 22 mmio_write_32(0x706312000 + (i * 4), 0x55555555); in erratum_a050426() 23 mmio_write_32(0x706312400 + (i * 4), 0x55555555); in erratum_a050426() 24 mmio_write_32(0x706312800 + (i * 4), 0x55555555); in erratum_a050426() 25 mmio_write_32(0x706314000 + (i * 4), 0x55555555); in erratum_a050426() 26 mmio_write_32(0x706314400 + (i * 4), 0x55555555); in erratum_a050426() 27 mmio_write_32(0x706314800 + (i * 4), 0x55555555); in erratum_a050426() 28 mmio_write_32(0x706314c00 + (i * 4), 0x55555555); in erratum_a050426() 413 mmio_write_32(0x700117E60, val3); in erratum_a050426() [all …]
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/trusted-firmware-a/plat/hisilicon/hikey/ |
A D | hikey_ddr.c | 26 mmio_write_32((0xf7032000 + 0x000), data); in init_pll() 34 mmio_write_32((0xf7800000 + 0x000), data); in init_pll() 58 mmio_write_32(0xf7032000 + 0x050, data); in init_pll() 81 mmio_write_32((0xf7032000 + 0x374), 0x4a); in init_freq() 82 mmio_write_32((0xf7032000 + 0x368), 0xda); in init_freq() 83 mmio_write_32((0xf7032000 + 0x36c), 0x01); in init_freq() 84 mmio_write_32((0xf7032000 + 0x370), 0x01); in init_freq() 85 mmio_write_32((0xf7032000 + 0x360), 0x60); in init_freq() 1218 mmio_write_32(0xf7030340, 0xa000); in ddr_phy_reset() 1219 mmio_write_32(0xf7030344, 0xa000); in ddr_phy_reset() [all …]
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/trusted-firmware-a/plat/hisilicon/hikey960/ |
A D | hikey960_bl_common.c | 18 mmio_write_32(0xfff350b4, 0xf0002000); in hikey960_clk_init() 20 mmio_write_32(0xfff350bc, 0xfc004c00); in hikey960_clk_init() 337 mmio_write_32(0xe8420364, ret); in isps_control_clock() 341 mmio_write_32(0xe8420364, ret); in isps_control_clock() 367 mmio_write_32(0xe8420374, ret); in set_isp_srt_power_up() 371 mmio_write_32(0xe8420010, ~0); in set_isp_srt_power_up() 389 mmio_write_32(0xe8583800, 0x7); in hikey960_regulator_enable() 391 mmio_write_32(0xe8583804, 0xf); in hikey960_regulator_enable() 425 mmio_write_32(IOMG_AO_011_REG, 0); in hikey960_pinmux_init() 429 mmio_write_32(IOMG_044_REG, 0); in hikey960_pinmux_init() [all …]
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/trusted-firmware-a/plat/intel/soc/common/soc/ |
A D | socfpga_system_manager.c | 21 mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 23 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 25 mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC), in enable_ns_peripheral_access() 38 mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC0), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 39 mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC1), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 40 mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC2), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 55 mmio_write_32(SOCFPGA_L4_PER_SCR(I2C0), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 56 mmio_write_32(SOCFPGA_L4_PER_SCR(I2C1), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 57 mmio_write_32(SOCFPGA_L4_PER_SCR(I2C2), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() 58 mmio_write_32(SOCFPGA_L4_PER_SCR(I2C3), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access() [all …]
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/trusted-firmware-a/plat/mediatek/mt8183/drivers/emi_mpu/ |
A D | emi_mpu.c | 52 mmio_write_32(EMI_MPU_APC0, 0); in emi_mpu_set_region_protection() 54 mmio_write_32(EMI_MPU_EA0, end); in emi_mpu_set_region_protection() 59 mmio_write_32(EMI_MPU_APC1, 0); in emi_mpu_set_region_protection() 61 mmio_write_32(EMI_MPU_EA1, end); in emi_mpu_set_region_protection() 66 mmio_write_32(EMI_MPU_APC2, 0); in emi_mpu_set_region_protection() 68 mmio_write_32(EMI_MPU_EA2, end); in emi_mpu_set_region_protection() 73 mmio_write_32(EMI_MPU_APC3, 0); in emi_mpu_set_region_protection() 80 mmio_write_32(EMI_MPU_APC4, 0); in emi_mpu_set_region_protection() 87 mmio_write_32(EMI_MPU_APC5, 0); in emi_mpu_set_region_protection() 94 mmio_write_32(EMI_MPU_APC6, 0); in emi_mpu_set_region_protection() [all …]
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/trusted-firmware-a/plat/mediatek/mt8173/drivers/spm/ |
A D | spm.c | 98 mmio_write_32(SPM_POWER_ON_VAL0, 0); in spm_register_init() 100 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_register_init() 110 mmio_write_32(SPM_PCM_IM_PTR, 0); in spm_register_init() 111 mmio_write_32(SPM_PCM_IM_LEN, 0); in spm_register_init() 152 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_init_pcm_register() 156 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_init_pcm_register() 169 mmio_write_32(SPM_PCM_PASR_DPD_2, 0); in spm_set_power_control() 246 mmio_write_32(SPM_PCM_IM_PTR, ptr); in spm_kick_im_to_fetch() 247 mmio_write_32(SPM_PCM_IM_LEN, len); in spm_kick_im_to_fetch() 282 mmio_write_32(SPM_PCM_WDT_TIMER_VAL, in spm_kick_pcm_to_run() [all …]
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A D | spm_mcdi.c | 250 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event() 277 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event() 283 mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0); in spm_mcdi_cpu_wake_up_event() 285 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event() 334 mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 1); in spm_mcdi_wfi_sel_enter() 335 mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 1); in spm_mcdi_wfi_sel_enter() 338 mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 1); in spm_mcdi_wfi_sel_enter() 339 mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 1); in spm_mcdi_wfi_sel_enter() 342 mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 1); in spm_mcdi_wfi_sel_enter() 343 mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 1); in spm_mcdi_wfi_sel_enter() [all …]
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/trusted-firmware-a/drivers/renesas/rzg/qos/G2M/ |
A D | qos_init_g2m_v10.c | 75 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); in qos_init_g2m_v10() 79 mmio_write_32(AXI_ADSPLCR2, 0x089A0000U); in qos_init_g2m_v10() 80 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); in qos_init_g2m_v10() 91 mmio_write_32(QOSCTRL_RAS, 0x00000028U); in qos_init_g2m_v10() 96 mmio_write_32(QOSCTRL_EC, 0x00000000U); in qos_init_g2m_v10() 98 mmio_write_32(QOSCTRL_FSS, 0x000003e8U); in qos_init_g2m_v10() 121 mmio_write_32(0xFD820808U, 0x00001234U); in qos_init_g2m_v10() 122 mmio_write_32(0xFD820800U, 0x00000006U); in qos_init_g2m_v10() 123 mmio_write_32(0xFD821800U, 0x00000006U); in qos_init_g2m_v10() 124 mmio_write_32(0xFD822800U, 0x00000006U); in qos_init_g2m_v10() [all …]
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A D | qos_init_g2m_v11.c | 150 mmio_write_32(QOSCTRL_SL_INIT, in qos_init_g2m_v11() 154 mmio_write_32(QOSCTRL_REF_ARS, in qos_init_g2m_v11() 181 mmio_write_32(GPU_ACT0, 0x00000000U); in qos_init_g2m_v11() 182 mmio_write_32(GPU_ACT1, 0x00000000U); in qos_init_g2m_v11() 183 mmio_write_32(GPU_ACT2, 0x00000000U); in qos_init_g2m_v11() 184 mmio_write_32(GPU_ACT3, 0x00000000U); in qos_init_g2m_v11() 187 mmio_write_32(RT_ACT0, 0x00000000U); in qos_init_g2m_v11() 188 mmio_write_32(RT_ACT1, 0x00000000U); in qos_init_g2m_v11() 200 mmio_write_32(QOSWT_WTREF, in qos_init_g2m_v11() 202 mmio_write_32(QOSWT_WTSET0, in qos_init_g2m_v11() [all …]
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A D | qos_init_g2m_v30.c | 144 mmio_write_32(QOSCTRL_RAS, 0x00000044U); in qos_init_g2m_v30() 147 mmio_write_32(QOSCTRL_FSS, 0x0000000AU); in qos_init_g2m_v30() 155 mmio_write_32(QOSCTRL_SL_INIT, in qos_init_g2m_v30() 158 mmio_write_32(QOSCTRL_REF_ARS, in qos_init_g2m_v30() 181 mmio_write_32(RT_ACT0, 0x00000000U); in qos_init_g2m_v30() 182 mmio_write_32(RT_ACT1, 0x00000000U); in qos_init_g2m_v30() 185 mmio_write_32(CPU_ACT0, 0x00000003U); in qos_init_g2m_v30() 186 mmio_write_32(CPU_ACT1, 0x00000003U); in qos_init_g2m_v30() 187 mmio_write_32(CPU_ACT2, 0x00000003U); in qos_init_g2m_v30() 188 mmio_write_32(CPU_ACT3, 0x00000003U); in qos_init_g2m_v30() [all …]
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/trusted-firmware-a/plat/rockchip/rk3288/drivers/secure/ |
A D | secure.c | 21 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass() 25 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass() 66 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config() 94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init() 106 mmio_write_32(CORE_AXI_BUS_BASE + CORE_AXI_SECURITY0, in secure_gic_init() 112 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in secure_timer_init() 136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), in secure_sgrf_init() 141 mmio_write_32(TZPC_BASE + TZPC_DECPROT1SET, 0xff); in secure_sgrf_init() 142 mmio_write_32(TZPC_BASE + TZPC_DECPROT2SET, 0xff); in secure_sgrf_init() 147 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in secure_sgrf_init() [all …]
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/trusted-firmware-a/plat/intel/soc/stratix10/soc/ |
A D | s10_clock_manager.c | 43 mmio_write_32(ALT_CLKMGR_MAINPLL + in config_clkmgr_handoff() 48 mmio_write_32(ALT_CLKMGR_PERPLL + in config_clkmgr_handoff() 62 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK, in config_clkmgr_handoff() 67 mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC0, in config_clkmgr_handoff() 84 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_FDBCK, in config_clkmgr_handoff() 89 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC0, in config_clkmgr_handoff() 91 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC1, in config_clkmgr_handoff() 183 mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EN, in config_clkmgr_handoff() 188 mmio_write_32(ALT_CLKMGR + ALT_CLKMGR_INTRCLR, in config_clkmgr_handoff() 193 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), in config_clkmgr_handoff() [all …]
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/trusted-firmware-a/plat/rockchip/rk3399/drivers/secure/ |
A D | secure.c | 21 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass() 25 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass() 74 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), in sgrf_ddr_rgn_config() 81 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_config() 92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_gate() 104 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_ungate() 138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), in secure_sgrf_init() 140 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), in secure_sgrf_init() 142 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), in secure_sgrf_init() 146 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), in secure_sgrf_init() [all …]
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/trusted-firmware-a/drivers/renesas/rzg/qos/G2H/ |
A D | qos_init_g2h_v30.c | 181 mmio_write_32(AXI_MMCR, 0x00010008U); in qos_init_g2h_v30() 182 mmio_write_32(AXI_TR3CR, 0x00010000U); in qos_init_g2h_v30() 186 mmio_write_32(RT_ACT0, 0x00000000U); in qos_init_g2h_v30() 187 mmio_write_32(RT_ACT1, 0x00000000U); in qos_init_g2h_v30() 190 mmio_write_32(CPU_ACT0, 0x00000003U); in qos_init_g2h_v30() 191 mmio_write_32(CPU_ACT1, 0x00000003U); in qos_init_g2h_v30() 192 mmio_write_32(CPU_ACT2, 0x00000003U); in qos_init_g2h_v30() 193 mmio_write_32(CPU_ACT3, 0x00000003U); in qos_init_g2h_v30() 199 mmio_write_32(QOSWT_WTREF, in qos_init_g2h_v30() 201 mmio_write_32(QOSWT_WTSET0, in qos_init_g2h_v30() [all …]
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/trusted-firmware-a/plat/rockchip/rk3368/drivers/soc/ |
A D | soc.c | 90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init() 93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init() 121 mmio_write_32(addr, tmp); in regs_updata_bits() 147 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), in plls_resume() 149 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), in plls_resume() 151 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in plls_resume() 153 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in plls_resume() 155 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), in plls_resume() 179 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in pm_plls_resume() 181 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in pm_plls_resume() [all …]
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/trusted-firmware-a/plat/imx/imx8m/imx8mm/ |
A D | gpc.c | 29 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init() 30 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init() 31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init() 33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init() 41 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init() 48 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); in imx_gpc_init() 61 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81); in imx_gpc_init() 62 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init() 66 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init() 79 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_gpc_init() [all …]
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/trusted-firmware-a/plat/imx/imx8m/imx8mn/ |
A D | gpc.c | 31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init() 32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init() 33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init() 35 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init() 43 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init() 63 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); in imx_gpc_init() 64 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init() 68 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init() 81 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_gpc_init() 92 mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3); in imx_gpc_init() [all …]
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/trusted-firmware-a/plat/rockchip/rk3328/drivers/pmu/ |
A D | pmu.c | 233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off() 336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume() 364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume() 383 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_suspend() 387 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_suspend() 429 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_resume() 475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend() 477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend() 485 mmio_write_32(GRF_BASE + PMIC_SLEEP_REG, in rk3328_pmic_resume() 602 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in sram_suspend() [all …]
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/trusted-firmware-a/plat/mediatek/mt8195/drivers/dfd/ |
A D | plat_dfd.c | 20 mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); in dfd_setup() 21 mmio_write_32(MTK_WDT_INTERVAL, MTK_WDT_INTERVAL_VAL); in dfd_setup() 62 mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); in dfd_setup() 65 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); in dfd_setup() 68 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); in dfd_setup() 71 mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); in dfd_setup() 74 mmio_write_32(DFD_TEST_SI_0, 0x0); in dfd_setup() 75 mmio_write_32(DFD_TEST_SI_1, 0x0); in dfd_setup() 76 mmio_write_32(DFD_TEST_SI_2, 0x0); in dfd_setup() 77 mmio_write_32(DFD_TEST_SI_3, 0x0); in dfd_setup() [all …]
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/trusted-firmware-a/drivers/renesas/common/pwrc/ |
A D | pwrc.c | 209 mmio_write_32(reg_cpumcr, 0); in scu_power_up() 228 mmio_write_32(reg_pwron, 1); in scu_power_up() 264 mmio_write_32(CPG_CPGWPR, ~on_data); in rcar_pwrc_cpuon() 265 mmio_write_32(on_reg, on_data); in rcar_pwrc_cpuon() 355 mmio_write_32(dst, MODE_L2_DOWN); in rcar_pwrc_clusteroff() 429 mmio_write_32(rst_barh, 0); in rcar_pwrc_setup() 473 mmio_write_32(DBSC4_REG_DBACEN, 0); in rcar_pwrc_set_self_refresh() 500 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh() 507 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh() 548 mmio_write_32(DBSC4_REG_DBACEN, 0); in rcar_pwrc_set_self_refresh_e3() [all …]
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/trusted-firmware-a/plat/rockchip/px30/drivers/secure/ |
A D | secure.c | 39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 52 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init() 59 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init() 84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); in sgrf_init() 85 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); in sgrf_init() 88 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); in sgrf_init() 91 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); in sgrf_init() 94 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); in sgrf_init() 100 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); in sgrf_init() [all …]
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/trusted-firmware-a/plat/imx/imx8m/imx8mp/ |
A D | gpc.c | 137 mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry); in imx_noc_qos() 213 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0); in imx_gpc_pm_domain_enable() 214 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x0); in imx_gpc_pm_domain_enable() 224 mmio_write_32(IMX_HSIOMIX_CTL_BASE, 0x2); in imx_gpc_pm_domain_enable() 291 mmio_write_32(IMX_HDMI_CTL_BASE + 0x40, 0x0); in imx_gpc_pm_domain_enable() 292 mmio_write_32(IMX_HDMI_CTL_BASE + 0x50, 0x0); in imx_gpc_pm_domain_enable() 322 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init() 343 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init() 347 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init() 361 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_gpc_init() [all …]
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