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Searched refs:mpidr (Results 1 – 25 of 239) sorted by relevance

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/trusted-firmware-a/plat/mediatek/mt6795/
A Dplat_pm.c76 cluster = get_cluster_data(mpidr); in get_core_data()
77 cpuid = mpidr & MPIDR_CPU_MASK; in get_core_data()
153 core = get_core_data(mpidr); in mt_cpu_save()
164 core = get_core_data(mpidr); in mt_cpu_restore()
171 mt_cpu_save(mpidr); in mt_platform_save_context()
177 mt_cpu_restore(mpidr); in mt_platform_restore_context()
253 cpu_id = mpidr & MPIDR_CPU_MASK; in plat_affinst_on()
326 cpu_id = mpidr & MPIDR_CPU_MASK; in plat_affinst_suspend()
343 disable_scu(mpidr); in plat_affinst_suspend()
371 enable_scu(mpidr); in plat_affinst_on_finish()
[all …]
A Dpower_tracer.c14 void trace_power_flow(unsigned long mpidr, unsigned char mode) in trace_power_flow() argument
19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
20 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
25 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
30 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
/trusted-firmware-a/drivers/arm/fvp/
A Dfvp_pwrc.c19 unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr) in fvp_pwrc_get_cpu_wkr() argument
21 return PSYSR_WK(fvp_pwrc_read_psysr(mpidr)); in fvp_pwrc_get_cpu_wkr()
24 unsigned int fvp_pwrc_read_psysr(u_register_t mpidr) in fvp_pwrc_read_psysr() argument
28 mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); in fvp_pwrc_read_psysr()
34 void fvp_pwrc_write_pponr(u_register_t mpidr) in fvp_pwrc_write_pponr() argument
41 void fvp_pwrc_write_ppoffr(u_register_t mpidr) in fvp_pwrc_write_ppoffr() argument
48 void fvp_pwrc_set_wen(u_register_t mpidr) in fvp_pwrc_set_wen() argument
52 (unsigned int) (PWKUPR_WEN | mpidr)); in fvp_pwrc_set_wen()
56 void fvp_pwrc_clr_wen(u_register_t mpidr) in fvp_pwrc_clr_wen() argument
60 (unsigned int) mpidr); in fvp_pwrc_clr_wen()
[all …]
/trusted-firmware-a/plat/amlogic/g12a/
A Dg12a_pm.c50 u_register_t mpidr = read_mpidr_el1(); in g12a_system_reset() local
69 g12a_pm_reset(mpidr); in g12a_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in g12a_system_off() local
91 g12a_pm_set_reset_addr(mpidr, 0); in g12a_system_off()
92 g12a_pm_reset(mpidr); in g12a_system_off()
120 aml_scpi_set_css_power_state(mpidr, in g12a_pwr_domain_on()
149 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_off() local
158 aml_scpi_set_css_power_state(mpidr, in g12a_pwr_domain_off()
166 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_pwr_down_wfi() local
189 g12a_pm_set_reset_addr(mpidr, 0); in g12a_pwr_domain_pwr_down_wfi()
[all …]
/trusted-firmware-a/plat/amlogic/gxl/
A Dgxl_pm.c50 u_register_t mpidr = read_mpidr_el1(); in gxl_system_reset() local
69 gxl_pm_reset(mpidr); in gxl_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in gxl_system_off() local
91 gxl_pm_set_reset_addr(mpidr, 0); in gxl_system_off()
92 gxl_pm_reset(mpidr); in gxl_system_off()
120 aml_scpi_set_css_power_state(mpidr, in gxl_pwr_domain_on()
149 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_off() local
158 aml_scpi_set_css_power_state(mpidr, in gxl_pwr_domain_off()
165 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_pwr_down_wfi() local
188 gxl_pm_set_reset_addr(mpidr, 0); in gxl_pwr_domain_pwr_down_wfi()
[all …]
/trusted-firmware-a/plat/mediatek/mt8173/
A Dpower_tracer.c14 void trace_power_flow(unsigned long mpidr, unsigned char mode) in trace_power_flow() argument
19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
20 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
25 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
30 (mpidr & MPIDR_CPU_MASK)); in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
A Dplat_pm.c120 cpuid = mpidr & MPIDR_CPU_MASK; in get_core_data()
211 core = get_core_data(mpidr); in mt_cpu_save()
222 core = get_core_data(mpidr); in mt_cpu_restore()
229 mt_cpu_save(mpidr); in mt_platform_save_context()
235 mt_cpu_restore(mpidr); in mt_platform_restore_context()
263 cpu_id = mpidr & MPIDR_CPU_MASK; in plat_power_domain_on()
275 spm_hotplug_on(mpidr); in plat_power_domain_on()
298 spm_hotplug_off(mpidr); in plat_power_domain_off()
329 cpu_id = mpidr & MPIDR_CPU_MASK; in plat_power_domain_suspend()
355 disable_scu(mpidr); in plat_power_domain_suspend()
[all …]
/trusted-firmware-a/plat/hisilicon/hikey/
A Dhikey_pm.c37 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on()
38 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on()
52 unsigned long mpidr; in hikey_pwr_domain_on_finish() local
55 mpidr = read_mpidr(); in hikey_pwr_domain_on_finish()
57 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on_finish()
78 unsigned long mpidr; in hikey_pwr_domain_off() local
81 mpidr = read_mpidr(); in hikey_pwr_domain_off()
83 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_off()
135 unsigned long mpidr; in hikey_pwr_domain_suspend_finish() local
143 mpidr = read_mpidr_el1(); in hikey_pwr_domain_suspend_finish()
[all …]
/trusted-firmware-a/plat/arm/common/
A Darm_topology.c17 int arm_check_mpidr(u_register_t mpidr) in arm_check_mpidr() argument
29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
34 cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) & in arm_check_mpidr()
36 cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & in arm_check_mpidr()
40 mpidr &= MPIDR_AFFINITY_MASK; in arm_check_mpidr()
41 if ((mpidr & valid_mask) != 0U) in arm_check_mpidr()
49 if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) in arm_check_mpidr()
53 if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) in arm_check_mpidr()
/trusted-firmware-a/plat/amlogic/axg/
A Daxg_pm.c31 unsigned int core = plat_calc_core_pos(mpidr); in axg_pm_set_reset_addr()
39 unsigned int core = plat_calc_core_pos(mpidr); in axg_pm_reset()
47 u_register_t mpidr = read_mpidr_el1(); in axg_system_reset() local
58 axg_pm_reset(mpidr, 0); in axg_system_reset()
68 u_register_t mpidr = read_mpidr_el1(); in axg_system_off() local
79 axg_pm_set_reset_addr(mpidr, 0); in axg_system_off()
80 axg_pm_reset(mpidr, 0); in axg_system_off()
92 aml_scpi_set_css_power_state(mpidr, in axg_pwr_domain_on()
113 u_register_t mpidr = read_mpidr_el1(); in axg_pwr_domain_off() local
120 axg_pm_reset(mpidr, -1); in axg_pwr_domain_off()
[all …]
/trusted-firmware-a/plat/marvell/armada/common/
A Dmarvell_topology.c44 int marvell_check_mpidr(u_register_t mpidr) in marvell_check_mpidr() argument
48 mpidr &= MPIDR_AFFINITY_MASK; in marvell_check_mpidr()
50 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK | in marvell_check_mpidr()
55 nb_id = MPIDR_AFFLVL3_VAL(mpidr); in marvell_check_mpidr()
56 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in marvell_check_mpidr()
57 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in marvell_check_mpidr()
78 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
80 if (marvell_check_mpidr(mpidr) == -1) in plat_core_pos_by_mpidr()
83 return plat_marvell_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_topology.c76 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) in plat_arm_get_cluster_core_count() argument
87 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
93 thread_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
94 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
95 clus_id = MPIDR_AFFLVL2_VAL(mpidr); in plat_core_pos_by_mpidr()
98 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
99 clus_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
109 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) in plat_core_pos_by_mpidr()
121 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
122 return (int) plat_arm_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/arm/board/arm_fpga/
A Dfpga_topology.c54 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
58 mpidr &= (MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); in plat_core_pos_by_mpidr()
59 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); in plat_core_pos_by_mpidr()
61 if ((MPIDR_AFFLVL2_VAL(mpidr) >= FPGA_MAX_CLUSTER_COUNT) || in plat_core_pos_by_mpidr()
62 (MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) || in plat_core_pos_by_mpidr()
63 (MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) { in plat_core_pos_by_mpidr()
64 ERROR ("Invalid mpidr: 0x%08x\n", (uint32_t)mpidr); in plat_core_pos_by_mpidr()
69 core_pos = plat_fpga_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/drivers/renesas/common/pwrc/
A Dpwrc.h42 void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
43 void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
44 void rcar_pwrc_clusteroff(uint64_t mpidr);
45 void rcar_pwrc_cpuoff(uint64_t mpidr);
46 void rcar_pwrc_cpuon(uint64_t mpidr);
47 int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr);
50 uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr);
51 uint32_t rcar_pwrc_status(uint64_t mpidr);
53 uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
/trusted-firmware-a/plat/mediatek/mt8173/drivers/spm/
A Dspm_mcdi.c304 static void spm_mcdi_wfi_sel_enter(unsigned long mpidr) in spm_mcdi_wfi_sel_enter() argument
306 int core_id_val = mpidr & MPIDR_CPU_MASK; in spm_mcdi_wfi_sel_enter()
355 static void spm_mcdi_wfi_sel_leave(unsigned long mpidr) in spm_mcdi_wfi_sel_leave() argument
357 int core_id_val = mpidr & MPIDR_CPU_MASK; in spm_mcdi_wfi_sel_leave()
409 unsigned long cpu_id = mpidr & MPIDR_CPU_MASK; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
485 spm_mcdi_wfi_sel_enter(mpidr); in spm_mcdi_prepare_for_off_state()
487 spm_mcdi_set_cputop_pwrctrl_for_cluster_off(mpidr); in spm_mcdi_prepare_for_off_state()
495 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_mcdi_finish_for_on_state()
496 (mpidr & MPIDR_CPU_MASK); in spm_mcdi_finish_for_on_state()
499 spm_mcdi_clear_cputop_pwrctrl_for_cluster_on(mpidr); in spm_mcdi_finish_for_on_state()
[all …]
/trusted-firmware-a/plat/mediatek/mt8195/
A Dplat_topology.c36 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
45 return plat_mediatek_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
48 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
50 if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) { in plat_core_pos_by_mpidr()
54 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/mediatek/mt8192/
A Dplat_topology.c41 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
47 if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { in plat_core_pos_by_mpidr()
50 return plat_mediatek_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
53 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
55 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { in plat_core_pos_by_mpidr()
59 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
60 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/renesas/common/
A Dplat_pm.c71 rcar_pwrc_cpuon(mpidr); in rcar_pwr_domain_on()
79 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish() local
86 rcar_program_mailbox(mpidr, 0); in rcar_pwr_domain_on_finish()
97 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_off() local
100 rcar_pwrc_cpuoff(mpidr); in rcar_pwr_domain_off()
107 rcar_pwrc_clusteroff(mpidr); in rcar_pwr_domain_off()
115 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend() local
121 rcar_pwrc_enable_interrupt_wakeup(mpidr); in rcar_pwr_domain_suspend()
123 rcar_pwrc_cpuoff(mpidr); in rcar_pwr_domain_suspend()
129 rcar_pwrc_clusteroff(mpidr); in rcar_pwr_domain_suspend()
[all …]
/trusted-firmware-a/plat/layerscape/common/
A Dls_topology.c14 int ls_check_mpidr(u_register_t mpidr) in ls_check_mpidr() argument
20 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in ls_check_mpidr()
21 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in ls_check_mpidr()
23 mpidr &= MPIDR_AFFINITY_MASK; in ls_check_mpidr()
24 if (mpidr & valid_mask) in ls_check_mpidr()
34 if (cpu_id >= plat_ls_get_cluster_core_count(mpidr)) in ls_check_mpidr()
/trusted-firmware-a/plat/amlogic/common/
A Daml_topology.c35 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
39 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
40 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
43 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
44 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
52 return plat_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/rpi/common/
A Drpi3_topology.c37 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
41 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
42 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { in plat_core_pos_by_mpidr()
46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
57 return plat_rpi3_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/qemu/common/
A Dtopology.c39 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
43 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
44 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
47 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
48 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
56 return plat_qemu_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/include/drivers/arm/fvp/
A Dfvp_pwrc.h45 void fvp_pwrc_write_pcoffr(u_register_t mpidr);
46 void fvp_pwrc_write_ppoffr(u_register_t mpidr);
47 void fvp_pwrc_write_pponr(u_register_t mpidr);
48 void fvp_pwrc_set_wen(u_register_t mpidr);
49 void fvp_pwrc_clr_wen(u_register_t mpidr);
50 unsigned int fvp_pwrc_read_psysr(u_register_t mpidr);
51 unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr);
/trusted-firmware-a/plat/qemu/qemu_sbsa/
A Dsbsa_topology.c39 int plat_core_pos_by_mpidr(u_register_t mpidr) in plat_core_pos_by_mpidr() argument
43 mpidr &= MPIDR_AFFINITY_MASK; in plat_core_pos_by_mpidr()
44 if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) { in plat_core_pos_by_mpidr()
49 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
50 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
62 return plat_qemu_calc_core_pos(mpidr); in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/allwinner/common/
A Dsunxi_cpu_ops.c49 static void sunxi_cpu_off(u_register_t mpidr) in sunxi_cpu_off() argument
51 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in sunxi_cpu_off()
52 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in sunxi_cpu_off()
67 void sunxi_cpu_on(u_register_t mpidr) in sunxi_cpu_on() argument
69 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in sunxi_cpu_on()
70 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in sunxi_cpu_on()
101 u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) | in sunxi_cpu_power_off_others() local
104 if (mpidr != self) in sunxi_cpu_power_off_others()
105 sunxi_cpu_off(mpidr); in sunxi_cpu_power_off_others()

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