| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
| A D | plat_sip_calls.c | 44 uint64_t per[3] = {0ULL}; in plat_sip_handler() local
63 per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U); in plat_sip_handler()
64 per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U); in plat_sip_handler()
65 per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U); in plat_sip_handler()
68 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); in plat_sip_handler()
69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
70 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); in plat_sip_handler()
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| /trusted-firmware-a/fdts/ |
| A D | fvp-base-gicv3-psci-1t.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
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| A D | fvp-base-gicv3-psci-aarch32-1t.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
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| A D | fvp-base-gicv3-psci-dynamiq-2t.dts | 7 /* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
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| A D | fvp-base-gicv3-psci-common.dtsi | 82 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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| A D | fvp-defs.dtsi | 337 /* Max 4 CPUs per cluster */
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/fconf/ |
| A D | mpmm-bindings.rst.txt | 5 DTB bindings allow the platform to communicate per-core support for |MPMM| via
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| /trusted-firmware-a/docs/components/fconf/ |
| A D | mpmm-bindings.rst | 5 DTB bindings allow the platform to communicate per-core support for |MPMM| via
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| /trusted-firmware-a/plat/nvidia/tegra/scat/ |
| A D | bl31.scat | 193 /* padded memory section to store per cpu bakery locks */
225 /* padded memory section to store per cpu timestamps */
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | mpmm.rst.txt | 11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
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| /trusted-firmware-a/docs/components/ |
| A D | mpmm.rst | 11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
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| /trusted-firmware-a/ |
| A D | .editorconfig | 66 # "Use 4 spaces per indentation level."
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| /trusted-firmware-a/docs/build/latex/ |
| A D | sphinxlatexnumfig.sty | 45 % LaTeX core per default does not reset chapter or section
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| /trusted-firmware-a/docs/design/ |
| A D | firmware-design.rst | 549 BL31 initializes the per-CPU data framework, which provides a cache of
973 Function ID is passed in W0 from the lower exception level (as per the
2125 Depending upon the data cache line size, the per-CPU fields of the
2175 | `bakery_info_t`| <-- Lock_0 per-CPU field
2178 | `bakery_info_t`| <-- Lock_1 per-CPU field
2183 | `bakery_info_t`| <-- Lock_N per-CPU field
2191 | `bakery_info_t`| <-- Lock_0 per-CPU field
2194 | `bakery_info_t`| <-- Lock_1 per-CPU field
2199 | `bakery_info_t`| <-- Lock_N per-CPU field
2496 PMF timestamps are stored in a per-service timestamp region. On a
[all …]
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| A D | interrupt-framework-design.rst | 328 interrupt was generated and routed as per the routing model specified
510 will be routed to EL3 (as per the routing model where **CSS=1 and
534 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
635 upon exception entry. The registers are saved in the per-cpu ``cpu_context``
639 per-cpu ``cpu_context`` data structure referenced by the ``SP_EL3`` register.
642 from the per-cpu ``cpu_context`` data structure in ``SP_EL0`` and
675 The handler function returns a reference to the per-cpu ``cpu_context_t``
728 per the synchronous interrupt handling model it implements. A Secure-EL1
735 #. Setting the return value of the handler to the per-cpu ``cpu_context`` if
787 #. It returns the per-cpu ``cpu_context`` to indicate that the interrupt can
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | firmware-design.rst.txt | 549 BL31 initializes the per-CPU data framework, which provides a cache of
973 Function ID is passed in W0 from the lower exception level (as per the
2125 Depending upon the data cache line size, the per-CPU fields of the
2175 | `bakery_info_t`| <-- Lock_0 per-CPU field
2178 | `bakery_info_t`| <-- Lock_1 per-CPU field
2183 | `bakery_info_t`| <-- Lock_N per-CPU field
2191 | `bakery_info_t`| <-- Lock_0 per-CPU field
2194 | `bakery_info_t`| <-- Lock_1 per-CPU field
2199 | `bakery_info_t`| <-- Lock_N per-CPU field
2496 PMF timestamps are stored in a per-service timestamp region. On a
[all …]
|
| A D | interrupt-framework-design.rst.txt | 328 interrupt was generated and routed as per the routing model specified
510 will be routed to EL3 (as per the routing model where **CSS=1 and
534 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
635 upon exception entry. The registers are saved in the per-cpu ``cpu_context``
639 per-cpu ``cpu_context`` data structure referenced by the ``SP_EL3`` register.
642 from the per-cpu ``cpu_context`` data structure in ``SP_EL0`` and
675 The handler function returns a reference to the per-cpu ``cpu_context_t``
728 per the synchronous interrupt handling model it implements. A Secure-EL1
735 #. Setting the return value of the handler to the per-cpu ``cpu_context`` if
787 #. It returns the per-cpu ``cpu_context`` to indicate that the interrupt can
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | poplar.rst.txt | 12 video at 60 frames per second.
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| A D | nvidia-tegra.rst.txt | 35 micro-ops can be executed per clock), and includes a 128KB 4-way L1
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| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 31 As per the `SMC Calling Convention`_, up to 4 values may be returned to the
|
| /trusted-firmware-a/docs/plat/ |
| A D | poplar.rst | 12 video at 60 frames per second.
|
| A D | nvidia-tegra.rst | 35 micro-ops can be executed per clock), and includes a 128KB 4-way L1
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-8.rst.txt | 31 As per the `SMC Calling Convention`_, up to 4 values may be returned to the
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/ |
| A D | porting.rst.txt | 113 The PHY porting layer simplifies updating static values per board type,
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| /trusted-firmware-a/docs/plat/marvell/armada/ |
| A D | porting.rst | 113 The PHY porting layer simplifies updating static values per board type,
|