| /trusted-firmware-a/drivers/nxp/ddr/phy-gen2/ |
| A D | phy.c | 148 uint16_t *phy; in get_cdd_val() local
157 phy = phy_ptr[i]; in get_cdd_val()
158 if (phy == NULL) { in get_cdd_val()
406 phy = phy_ptr[j]; in save_phy_training_values()
483 phy = phy_ptr[j]; in restore_phy_training_values()
716 uint16_t *phy; in i_load_pie() local
719 phy = phy_ptr[i]; in i_load_pie()
720 if (phy == NULL) { in i_load_pie()
1874 uint16_t *phy; in c_init_phy_config() local
2125 uint16_t *phy; in g_exec_fw() local
[all …]
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| /trusted-firmware-a/plat/rockchip/rk3368/drivers/ddr/ |
| A D | ddr_rk3368.c | 169 struct DDRPHY_SAVE_REG_TAG phy; member
343 p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
348 p_ddr_reg->phy.PHY_REGEF = 0; in ddr_reg_save()
351 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
353 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
355 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
357 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
360 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
362 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
364 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE + in ddr_reg_save()
[all …]
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| /trusted-firmware-a/plat/brcm/board/stingray/driver/ |
| A D | usb_phy.c | 278 usb_phy_t *phy = phy_port->p; in u3h_u2drd_phy_reset() local
288 mmio_clrbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
290 mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
298 usb_phy_t *phy = phy_port->p; in u3drd_phy_reset() local
310 usb_phy_t *phy = phy_port->p; in u3h_u2drd_phy_power_on() local
317 status = usb3h_u3_phy_power_on(phy->usb3hreg); in u3h_u2drd_phy_power_on()
336 status = usb3h_u2_phy_power_on(phy->usb3hreg); in u3h_u2drd_phy_power_on()
356 status = drdu2_u2_phy_power_on(phy->drdu2reg); in u3h_u2drd_phy_power_on()
388 usb_phy_t *phy = phy_port->p; in u3drd_phy_power_on() local
396 status = drdu3_u3_phy_power_on(phy->drdu3reg); in u3drd_phy_power_on()
[all …]
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| /trusted-firmware-a/drivers/st/ddr/ |
| A D | stm32mp1_ddr.c | 292 return (uintptr_t)priv->phy; in get_base_addr()
330 pgsr = mmio_read_32((uintptr_t)&phy->pgsr); in stm32mp1_ddrphy_idone_wait()
333 (uintptr_t)&phy->pgsr, pgsr); in stm32mp1_ddrphy_idone_wait()
365 (uintptr_t)&phy->pgsr, pgsr); in stm32mp1_ddrphy_idone_wait()
374 (uintptr_t)&phy->pir, pir_init, in stm32mp1_ddrphy_init()
375 mmio_read_32((uintptr_t)&phy->pir)); in stm32mp1_ddrphy_init()
381 stm32mp1_ddrphy_idone_wait(phy); in stm32mp1_ddrphy_init()
823 (uintptr_t)&priv->phy->mr1, in stm32mp1_ddr_init()
831 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
846 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
[all …]
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| A D | stm32mp1_ram.c | 293 priv->phy = (struct stm32mp1_ddrphy *)stm32mp_ddrphyc_base(); in stm32mp1_ddr_probe()
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/ |
| A D | porting.rst.txt | 101 Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
124 ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
126 phy-porting-layer.h file under: ``plat/marvell/armada/<soc
127 family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
128 exists, the phy-default-porting-layer.h is not going to be included.
138 …``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<pla…
148 ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
152 phy-porting-layer.h), the default values are used
153 (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is
|
| /trusted-firmware-a/docs/plat/marvell/armada/ |
| A D | porting.rst | 101 Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
124 ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
126 phy-porting-layer.h file under: ``plat/marvell/armada/<soc
127 family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
128 exists, the phy-default-porting-layer.h is not going to be included.
138 …``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<pla…
148 ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
152 phy-porting-layer.h), the default values are used
153 (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is
|
| /trusted-firmware-a/fdts/ |
| A D | stm32mp15-ddr.dtsi | 86 st,phy-reg = <
100 st,phy-timing = <
113 st,phy-cal = <
|
| A D | stm32mp15xx-dkx.dtsi | 334 phy-names = "usb2-phy";
344 phy-supply = <&vdd_usb>;
348 phy-supply = <&vdd_usb>;
|
| A D | corstone700_fpga.dts | 17 phy-mode = "mii";
|
| A D | corstone700_fvp.dts | 30 phy-mode = "mii";
|
| A D | stm32mp151.dtsi | 391 usbphyc_port0: usb-phy@0 {
392 #phy-cells = <0>;
396 usbphyc_port1: usb-phy@1 {
397 #phy-cells = <1>;
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| A D | a5ds.dts | 153 phy-mode = "mii";
|
| /trusted-firmware-a/drivers/nxp/ddr/nxp-ddr/ |
| A D | ddr.mk | 9 PLAT_DDR_PHY_DIR := phy-gen2
25 PLAT_DDR_PHY_DIR := phy-gen1
74 $(PLAT_DRIVERS_PATH)/ddr/$(PLAT_DDR_PHY_DIR)/phy.c
|
| A D | utility.c | 145 priv->phy[0] = priv->phy[0]; in disable_unused_ddrc()
146 priv->phy[1] = NULL; in disable_unused_ddrc()
152 priv->phy[1] = NULL; in disable_unused_ddrc()
|
| /trusted-firmware-a/plat/nxp/soc-lx2160a/lx2160ardb/ |
| A D | ddr_init.c | 188 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr()
189 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr()
|
| /trusted-firmware-a/include/drivers/nxp/ddr/ |
| A D | ddr.h | 98 uint16_t *phy[MAX_DDRC_NUM]; member
|
| /trusted-firmware-a/plat/nxp/soc-lx2160a/ |
| A D | ddr_fip.mk | 7 DDR_PHY_BIN_PATH ?= ./ddr-phy-binary/lx2160a
|
| /trusted-firmware-a/plat/nxp/soc-lx2160a/lx2160aqds/ |
| A D | ddr_init.c | 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr()
324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr()
|
| /trusted-firmware-a/plat/nxp/soc-lx2160a/lx2162aqds/ |
| A D | ddr_init.c | 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr()
324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr()
|
| /trusted-firmware-a/docs/plat/nxp/ |
| A D | nxp-layerscape.rst | 139 - ddr-phy-binary: Required by platforms that need fip-ddr.
140 `link <https:://github.com/NXP/ddr-phy-binary>`__
161 - Copy/clone the repo "ddr-phy-binary" to the tfa directory for platform needing ddr-fip.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/nxp/ |
| A D | nxp-layerscape.rst.txt | 139 - ddr-phy-binary: Required by platforms that need fip-ddr.
140 `link <https:://github.com/NXP/ddr-phy-binary>`__
161 - Copy/clone the repo "ddr-phy-binary" to the tfa directory for platform needing ddr-fip.
|
| /trusted-firmware-a/include/drivers/st/ |
| A D | stm32mp1_ddr.h | 32 struct stm32mp1_ddrphy *phy; member
|
| /trusted-firmware-a/plat/rockchip/rk3399/drivers/dram/ |
| A D | suspend.c | 126 uint32_t phy) in rkclk_ddr_reset() argument
130 phy &= 0x1; in rkclk_ddr_reset()
133 CRU_SFTRST_DDR_PHY(channel, phy)); in rkclk_ddr_reset()
|
| /trusted-firmware-a/plat/marvell/armada/a8k/common/ |
| A D | a8k_common.mk | 123 $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
|