Searched refs:phys_base (Results 1 – 6 of 6) sorted by relevance
| /trusted-firmware-a/plat/nvidia/tegra/drivers/memctrl/ |
| A D | memctrl_v2.c | 102 plat_memctrl_tzdram_setup(phys_base, size_in_bytes); in tegra_memctrl_tzdram_setup()
171 static void tegra_lock_videomem_nonoverlap(uint64_t phys_base, in tegra_lock_videomem_nonoverlap() argument
192 assert((phys_base & (uint64_t)0xFFF) == 0U); in tegra_lock_videomem_nonoverlap()
260 uintptr_t vmem_end_new = phys_base + size_in_bytes; in tegra_clear_videomem_nonoverlap()
275 if (video_mem_base < phys_base) { in tegra_clear_videomem_nonoverlap()
276 non_overlap_area_size = phys_base - video_mem_base; in tegra_clear_videomem_nonoverlap()
315 (uint32_t)(phys_base >> 32)); in tegra_memctrl_videomem_setup()
320 == (uint32_t)phys_base); in tegra_memctrl_videomem_setup()
322 == (uint32_t)(phys_base >> 32)); in tegra_memctrl_videomem_setup()
334 tegra_clear_videomem_nonoverlap(phys_base, size_in_bytes); in tegra_memctrl_videomem_setup()
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| A D | memctrl_v1.c | 84 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) in tegra_memctrl_tzdram_setup() argument
92 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); in tegra_memctrl_tzdram_setup()
124 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) in tegra_memctrl_videomem_setup() argument
127 uintptr_t vmem_end_new = phys_base + size_in_bytes; in tegra_memctrl_videomem_setup()
152 if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { in tegra_memctrl_videomem_setup()
155 if (video_mem_base < phys_base) { in tegra_memctrl_videomem_setup()
156 non_overlap_area_size = phys_base - video_mem_base; in tegra_memctrl_videomem_setup()
166 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32)); in tegra_memctrl_videomem_setup()
167 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); in tegra_memctrl_videomem_setup()
171 video_mem_base = phys_base; in tegra_memctrl_videomem_setup()
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
| A D | plat_memctrl.c | 54 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) in plat_memctrl_tzdram_setup() argument
57 uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; in plat_memctrl_tzdram_setup()
58 uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); in plat_memctrl_tzdram_setup()
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| /trusted-firmware-a/plat/nvidia/tegra/include/drivers/ |
| A D | memctrl.h | 13 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
14 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
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| A D | memctrl_v2.h | 103 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t186/ |
| A D | plat_memctrl.c | 664 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) in plat_memctrl_tzdram_setup() argument
674 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); in plat_memctrl_tzdram_setup()
675 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); in plat_memctrl_tzdram_setup()
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