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Searched refs:plat_params (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a/plat/nvidia/tegra/soc/t210/
A Dplat_setup.c175 (uint32_t)plat_params->tzdram_size); in plat_early_platform_setup()
178 if (plat_params->l2_ecc_parity_prot_dis != 1) { in plat_early_platform_setup()
210 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { in plat_late_platform_setup()
221 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); in plat_late_platform_setup()
223 sc7entry_end = plat_params->sc7entry_fw_base + in plat_late_platform_setup()
224 plat_params->sc7entry_fw_size; in plat_late_platform_setup()
225 assert(sc7entry_end < plat_params->tzdram_base); in plat_late_platform_setup()
228 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in plat_late_platform_setup()
233 plat_params->tzdram_size + offset); in plat_late_platform_setup()
240 plat_params->sc7entry_fw_base, in plat_late_platform_setup()
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A Dplat_psci_handlers.c47 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_validate_power_state() local
75 if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) in tegra_soc_validate_power_state()
347 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi() local
409 (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES), in tegra_soc_pwr_domain_power_down_wfi()
410 plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES); in tegra_soc_pwr_domain_power_down_wfi()
435 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish() local
441 if (plat_params->l2_ecc_parity_prot_dis != 1) { in tegra_soc_pwr_domain_on_finish()
489 if (plat_params->sc7entry_fw_base != 0U) { in tegra_soc_pwr_domain_on_finish()
491 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in tegra_soc_pwr_domain_on_finish()
492 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, in tegra_soc_pwr_domain_on_finish()
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/trusted-firmware-a/plat/nvidia/tegra/common/
A Dtegra_bl31_setup.c96 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; in bl31_early_platform_setup2() local
107 if (plat_params == NULL) { in bl31_early_platform_setup2()
108 plat_params = plat_get_bl31_plat_params(); in bl31_early_platform_setup2()
130 assert(plat_params != NULL); in bl31_early_platform_setup2()
131 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; in bl31_early_platform_setup2()
132 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; in bl31_early_platform_setup2()
133 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; in bl31_early_platform_setup2()
150 plat_enable_console(plat_params->uart_id); in bl31_early_platform_setup2()
157 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, in bl31_early_platform_setup2()
163 plat_params->boot_profiler_shmem_base; in bl31_early_platform_setup2()
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A Dtegra_pm.c156 const plat_params_from_bl2_t *plat_params; in tegra_pwr_domain_on_finish() local
183 plat_params = bl31_get_plat_params(); in tegra_pwr_domain_on_finish()
184 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in tegra_pwr_domain_on_finish()
185 (uint32_t)plat_params->tzdram_size); in tegra_pwr_domain_on_finish()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_setup.c189 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup() local
201 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in plat_early_platform_setup()
202 (uint32_t)plat_params->tzdram_size); in plat_early_platform_setup()
210 if ((plat_params->l2_ecc_parity_prot_dis != 1) && in plat_early_platform_setup()
A Dplat_psci_handlers.c376 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish() local
384 if ((plat_params->l2_ecc_parity_prot_dis != 1) && (impl != DENVER_IMPL)) { in tegra_soc_pwr_domain_on_finish()

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