| /trusted-firmware-a/plat/rockchip/rk3399/drivers/gpio/ |
| A D | rk3399_gpio.c | 73 assert(port < 5); in gpio_get_clock()
75 switch (port) { in gpio_get_clock()
128 switch (port) { in gpio_put_clock()
167 assert((port < 5) && (bank < 4)); in get_pull()
171 if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) { in get_pull()
173 port * 16 + bank * 4); in get_pull()
190 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { in get_pull()
209 assert((port < 5) && (bank < 4)); in set_pull()
221 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { in set_pull()
230 if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) { in set_pull()
[all …]
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| /trusted-firmware-a/include/dt-bindings/pinctrl/ |
| A D | stm32-pinfunc.h | 32 #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) argument
34 #define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) argument
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| /trusted-firmware-a/plat/allwinner/common/ |
| A D | sunxi_common.c | 84 void sunxi_set_gpio_out(char port, int pin, bool level_high) in sunxi_set_gpio_out() argument
88 if (port < 'A' || port > 'L') in sunxi_set_gpio_out()
90 if (port == 'L') in sunxi_set_gpio_out()
93 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; in sunxi_set_gpio_out()
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| /trusted-firmware-a/plat/hisilicon/hikey/ |
| A D | hikey_security.c | 51 static volatile struct rgn_map_reg *get_rgn_map_reg(uint32_t base, int region, int port) in get_rgn_map_reg() argument
53 uint64_t addr = base + 0x100 + 0x10 * region + 0x400 * (uint64_t)port; in get_rgn_map_reg()
58 int port) in get_rgn_attr_reg() argument
60 uint64_t addr = base + 0x104 + 0x10 * region + 0x400 * (uint64_t)port; in get_rgn_attr_reg()
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| A D | hikey_ddr.c | 1357 unsigned int port, data; in init_ddrc_qos() local
1361 port = 0; in init_ddrc_qos()
1362 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); in init_ddrc_qos()
1367 for (port = 3; port <= 4; port++) { in init_ddrc_qos()
1368 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); in init_ddrc_qos()
1373 port = 1; in init_ddrc_qos()
1374 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000); in init_ddrc_qos()
1375 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567); in init_ddrc_qos()
1376 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567); in init_ddrc_qos()
1394 port = 2; in init_ddrc_qos()
[all …]
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| /trusted-firmware-a/plat/brcm/board/stingray/src/ |
| A D | bl31_setup.c | 185 #define SATA_APBT_IDM_PORT_REG(port, reg) \ argument
186 (((port/4) << 12) + reg)
188 #define SATA_IDM_PORT_REG(port, reg) ((port << 12) + reg) argument
190 #define SATA_PORT_REG(port, reg) \ argument
191 (((port%4) << 16) + ((port/4) << 20) + reg)
201 static uint32_t brcm_stingray_get_sata_port(unsigned int port) in brcm_stingray_get_sata_port() argument
203 return sr_b0_sata_port[port]; in brcm_stingray_get_sata_port()
208 unsigned int port = 0; in brcm_stingray_sata_init() local
217 for (port = 0; port < USE_SATA_PORTS; port++) { in brcm_stingray_sata_init()
219 sata_port = brcm_stingray_get_sata_port(port); in brcm_stingray_sata_init()
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| /trusted-firmware-a/docs/plat/ |
| A D | meson-axg.rst | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
23 This port has been tested on a A113D board. After building it, follow the
25 by the one built from this port.
|
| A D | meson-g12a.rst | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested on a SEI510 board. After building it, follow the
24 mentioned **bl31.img** by the one built from this port.
|
| A D | meson-gxbb.rst | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested in a ODROID-C2. After building it, follow the
24 by the one built from this port.
|
| A D | meson-gxl.rst | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested on a Lepotato. After building it, follow the
24 mentioned **bl31.img** by the one built from this port.
|
| A D | rpi4.rst | 8 This port is a minimal port to support loading non-secure EL2 payloads such
12 **IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
51 TF-A port design
54 In contrast to the existing Raspberry Pi 3 port this one here is a BL31-only
55 port, also it deviates quite a lot from the RPi3 port in many other ways.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | meson-axg.rst.txt | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
23 This port has been tested on a A113D board. After building it, follow the
25 by the one built from this port.
|
| A D | meson-g12a.rst.txt | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested on a SEI510 board. After building it, follow the
24 mentioned **bl31.img** by the one built from this port.
|
| A D | meson-gxbb.rst.txt | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested in a ODROID-C2. After building it, follow the
24 by the one built from this port.
|
| A D | meson-gxl.rst.txt | 7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested on a Lepotato. After building it, follow the
24 mentioned **bl31.img** by the one built from this port.
|
| A D | rpi4.rst.txt | 8 This port is a minimal port to support loading non-secure EL2 payloads such
12 **IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
51 TF-A port design
54 In contrast to the existing Raspberry Pi 3 port this one here is a BL31-only
55 port, also it deviates quite a lot from the RPi3 port in many other ways.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst.txt | 13 - **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
17 - **0x5** = PCIe port
43 {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
|
| /trusted-firmware-a/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 13 - **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
17 - **0x5** = PCIe port
43 {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/about/ |
| A D | maintainers.rst.txt | 61 Armv7-A architecture port
389 Arm FPGA platform port
397 Arm FVP Platform port
405 Arm Juno Platform port
555 QEMU platform port
562 QTI platform port
622 RockChip platform port
633 STM32MP1 platform port
645 Synquacer platform port
659 UniPhier platform port
[all …]
|
| /trusted-firmware-a/docs/about/ |
| A D | maintainers.rst | 61 Armv7-A architecture port
389 Arm FPGA platform port
397 Arm FVP Platform port
405 Arm Juno Platform port
555 QEMU platform port
562 QTI platform port
622 RockChip platform port
633 STM32MP1 platform port
645 Synquacer platform port
659 UniPhier platform port
[all …]
|
| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.aux | 136 \newlabel{about/maintainers:arm-fpga-platform-port}{{1.3.2}{14}{Arm FPGA platform port}{paragraph*.…
138 \newlabel{about/maintainers:arm-fvp-platform-port}{{1.3.2}{14}{Arm FVP Platform port}{paragraph*.46…
140 \newlabel{about/maintainers:arm-juno-platform-port}{{1.3.2}{14}{Arm Juno Platform port}{paragraph*.…
166 \newlabel{about/maintainers:nxp-i-mx-8-platform-port}{{1.3.2}{17}{NXP i.MX 8 platform port}{paragra…
174 \newlabel{about/maintainers:qemu-platform-port}{{1.3.2}{18}{QEMU platform port}{paragraph*.64}{}}
176 \newlabel{about/maintainers:qti-platform-port}{{1.3.2}{18}{QTI platform port}{paragraph*.65}{}}
186 \newlabel{about/maintainers:rockchip-platform-port}{{1.3.2}{20}{RockChip platform port}{paragraph*.…
188 \newlabel{about/maintainers:stm32mp1-platform-port}{{1.3.2}{20}{STM32MP1 platform port}{paragraph*.…
190 \newlabel{about/maintainers:synquacer-platform-port}{{1.3.2}{21}{Synquacer platform port}{paragraph…
194 \newlabel{about/maintainers:uniphier-platform-port}{{1.3.2}{21}{UniPhier platform port}{paragraph*.…
[all …]
|
| /trusted-firmware-a/ |
| A D | .gitreview | 3 port=29418
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/arm_fpga/ |
| A D | index.rst.txt | 7 this port ignores any power management features of the platform.
15 As a result this port is a fairly generic BL31-only port, which can serve
16 as a template for a minimal new (and possibly DT-based) platform port.
18 The aim of this port is to support as many FPGA images as possible with
|
| /trusted-firmware-a/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 7 this port ignores any power management features of the platform.
15 As a result this port is a fairly generic BL31-only port, which can serve
16 as a template for a minimal new (and possibly DT-based) platform port.
18 The aim of this port is to support as many FPGA images as possible with
|
| /trusted-firmware-a/fdts/ |
| A D | n1sdp-single-chip.dts | 54 port {
73 port {
|