| /trusted-firmware-a/bl31/ |
| A D | ehf.c | 111 if (priority >= run_pri) { in ehf_activate_priority()
113 run_pri, priority); in ehf_activate_priority()
123 idx = pri_to_idx(priority); in ehf_activate_priority()
127 priority, IDX_TO_PRI(cur_pri_idx)); in ehf_activate_priority()
140 if (priority >= old_mask) { in ehf_activate_priority()
142 priority, old_mask); in ehf_activate_priority()
178 if (priority >= run_pri) { in ehf_deactivate_priority()
180 run_pri, priority); in ehf_deactivate_priority()
190 idx = pri_to_idx(priority); in ehf_deactivate_priority()
211 if (old_mask > priority) { in ehf_deactivate_priority()
[all …]
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | exception-handling.rst.txt | 90 is based on a priority scheme. This priority scheme is closely tied to how the
107 A priority level is *active* when a handler at that priority level is currently
122 and involves GIC priority masking, it's impossible for a lower priority
124 lower priority dispatcher cannot preempt a higher-priority one. Priority
175 Partitioning priority levels
181 priority assignment:
229 Programming priority
366 A priority level is said to be *active* when an exception of that priority is
433 Transition of priority levels
516 `Programming priority`_.
[all …]
|
| A D | sdei.rst.txt | 84 - Event priority: ``SDEI_MAPF_CRITICAL`` or ``SDEI_MAPF_NORMAL``, as described
136 - ``SDEI_MAPF_NORMAL``: Marks the event as having *Normal* priority. This is
137 the default priority.
139 - ``SDEI_MAPF_CRITICAL``: Marks the event as having *Critical* priority.
181 - Install priority descriptors for Normal and Critical SDEI interrupts.
268 - The priority of the event (either Critical or Normal, as configured by the
269 platform at build-time) shouldn't cause priority inversion. This means:
271 - If it's of Normal priority, neither Normal nor Critical priority dispatch
274 - If it's of a Critical priority, no Critical priority dispatch must be
285 priority so as not to cause priority level inversion within Exception
|
| A D | platform-interrupt-controller-API.rst.txt | 17 This API should return the priority of the interrupt the PE is currently
22 is read to determine the priority of the interrupt.
108 Function: void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); [optional]
117 This API should set the priority of the interrupt specified by first parameter
118 ``id`` to the value set by the second parameter ``priority``.
121 writes to GIC *Priority Register* set interrupt priority.
279 This API should set the priority mask (first parameter) in the interrupt
280 controller such that only interrupts of higher priority than the supplied one
281 may be signalled to the PE. The API should return the current priority value
|
| A D | ras.rst.txt | 227 means that the platform must partition a :ref:`priority level <Partitioning
228 priority levels>` for handling RAS exceptions. The platform must then define
229 the macro ``PLAT_RAS_PRI`` to the priority level used for RAS exceptions.
230 Platforms would typically want to allocate the highest secure priority for
235 documentation. I.e., for interrupts, the priority management is implicit; but
|
| A D | ffa-manifest-binding.rst.txt | 242 - Interrupt priority value
|
| /trusted-firmware-a/docs/components/ |
| A D | exception-handling.rst | 90 is based on a priority scheme. This priority scheme is closely tied to how the
107 A priority level is *active* when a handler at that priority level is currently
122 and involves GIC priority masking, it's impossible for a lower priority
124 lower priority dispatcher cannot preempt a higher-priority one. Priority
175 Partitioning priority levels
181 priority assignment:
229 Programming priority
366 A priority level is said to be *active* when an exception of that priority is
433 Transition of priority levels
516 `Programming priority`_.
[all …]
|
| A D | sdei.rst | 84 - Event priority: ``SDEI_MAPF_CRITICAL`` or ``SDEI_MAPF_NORMAL``, as described
136 - ``SDEI_MAPF_NORMAL``: Marks the event as having *Normal* priority. This is
137 the default priority.
139 - ``SDEI_MAPF_CRITICAL``: Marks the event as having *Critical* priority.
181 - Install priority descriptors for Normal and Critical SDEI interrupts.
268 - The priority of the event (either Critical or Normal, as configured by the
269 platform at build-time) shouldn't cause priority inversion. This means:
271 - If it's of Normal priority, neither Normal nor Critical priority dispatch
274 - If it's of a Critical priority, no Critical priority dispatch must be
285 priority so as not to cause priority level inversion within Exception
|
| A D | platform-interrupt-controller-API.rst | 17 This API should return the priority of the interrupt the PE is currently
22 is read to determine the priority of the interrupt.
108 Function: void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); [optional]
117 This API should set the priority of the interrupt specified by first parameter
118 ``id`` to the value set by the second parameter ``priority``.
121 writes to GIC *Priority Register* set interrupt priority.
279 This API should set the priority mask (first parameter) in the interrupt
280 controller such that only interrupts of higher priority than the supplied one
281 may be signalled to the PE. The API should return the current priority value
|
| A D | ras.rst | 227 means that the platform must partition a :ref:`priority level <Partitioning
228 priority levels>` for handling RAS exceptions. The platform must then define
229 the macro ``PLAT_RAS_PRI`` to the priority level used for RAS exceptions.
230 Platforms would typically want to allocate the highest secure priority for
235 documentation. I.e., for interrupts, the priority management is implicit; but
|
| A D | ffa-manifest-binding.rst | 242 - Interrupt priority value
|
| /trusted-firmware-a/include/bl31/ |
| A D | ehf.h | 28 #define EHF_PRI_DESC(plat_bits, priority) \ argument
29 [EHF_PRI_TO_IDX(priority, plat_bits)] = { \
84 void ehf_activate_priority(unsigned int priority);
85 void ehf_deactivate_priority(unsigned int priority);
|
| /trusted-firmware-a/plat/common/ |
| A D | plat_gicv2.c | 188 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) in plat_ic_set_interrupt_priority() argument
190 gicv2_set_interrupt_priority(id, priority); in plat_ic_set_interrupt_priority()
|
| A D | plat_gicv3.c | 219 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) in plat_ic_set_interrupt_priority() argument
221 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); in plat_ic_set_interrupt_priority()
|
| /trusted-firmware-a/services/std_svc/sdei/ |
| A D | sdei_private.h | 30 # error Platform must define SDEI critical priority value
34 # error Platform must define SDEI normal priority value
|
| /trusted-firmware-a/lib/extensions/ras/ |
| A D | ras_common.c | 19 # error Platform must define RAS priority value
|
| /trusted-firmware-a/include/drivers/arm/ |
| A D | gicv2.h | 178 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
|
| A D | gicv3.h | 536 unsigned int priority);
|
| /trusted-firmware-a/drivers/arm/gic/v2/ |
| A D | gicv2_main.c | 379 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) in gicv2_set_interrupt_priority() argument
385 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); in gicv2_set_interrupt_priority()
|
| /trusted-firmware-a/include/plat/common/ |
| A D | platform.h | 102 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority);
|
| /trusted-firmware-a/drivers/arm/gic/v3/ |
| A D | gicv3_main.c | 1009 unsigned int priority) in gicv3_set_interrupt_priority() argument
1022 gicr_set_ipriorityr(gicr_base, id, priority); in gicv3_set_interrupt_priority()
1025 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); in gicv3_set_interrupt_priority()
|
| /trusted-firmware-a/fdts/ |
| A D | fvp-base-gicv3-psci-common.dtsi | 85 * 2. Interrupt priority
|
| /trusted-firmware-a/docs/getting_started/ |
| A D | porting-guide.rst | 1934 - Configure the priority mask register to allow interrupts of all priorities
2080 This macro must be defined to the EL3 exception priority level associated with
2082 (therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
2087 This macro must be defined to the EL3 exception priority level associated with
2089 (therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
2092 priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2093 be higher than Normal |SDEI| priority.
2700 This API returns the type of the highest priority pending interrupt at the
2733 This API returns the id of the highest priority pending interrupt at the
2783 priority pending interrupt from pending to active in the interrupt controller.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | porting-guide.rst.txt | 1934 - Configure the priority mask register to allow interrupts of all priorities
2080 This macro must be defined to the EL3 exception priority level associated with
2082 (therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
2087 This macro must be defined to the EL3 exception priority level associated with
2089 (therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
2092 priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2093 be higher than Normal |SDEI| priority.
2700 This API returns the type of the highest priority pending interrupt at the
2733 This API returns the id of the highest priority pending interrupt at the
2783 priority pending interrupt from pending to active in the interrupt controller.
|
| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.tex | 14856 is based on a priority scheme. This priority scheme is closely tied to how the
14865 for more than one priority level.
14887 and involves GIC priority masking, it’s impossible for a lower priority
14889 lower priority dispatcher cannot preempt a higher\sphinxhyphen{}priority one. Priority
14956 priority assignment:
15451 priority level. This also has the effect of raising GIC priority mask, thus
17917 the default priority.
18099 If it’s of Normal priority, neither Normal nor Critical priority dispatch
18104 If it’s of a Critical priority, no Critical priority dispatch must be
18124 priority so as not to cause priority level inversion within Exception
[all …]
|