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Searched refs:pwr_domain_state (Results 1 – 25 of 59) sorted by relevance

123

/trusted-firmware-a/plat/nxp/common/psci/
A Dplat_psci.c183 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend()
194 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend()
258 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend_finish()
348 state->pwr_domain_state[PLAT_MAX_LVL] = in _pwr_state_validate()
351 state->pwr_domain_state[PLAT_MAX_LVL] = in _pwr_state_validate()
356 state->pwr_domain_state[PLAT_SYS_LVL] = in _pwr_state_validate()
359 state->pwr_domain_state[PLAT_SYS_LVL] = in _pwr_state_validate()
364 state->pwr_domain_state[PLAT_CLSTR_LVL] = in _pwr_state_validate()
367 state->pwr_domain_state[PLAT_CLSTR_LVL] = in _pwr_state_validate()
374 state->pwr_domain_state[PLAT_CORE_LVL] = in _pwr_state_validate()
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/trusted-firmware-a/plat/xilinx/versal/
A Dplat_psci.c58 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend()
62 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
66 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in versal_pwr_domain_suspend()
74 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
94 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend_finish()
103 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend_finish()
159 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_off()
196 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
198 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
214 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
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/trusted-firmware-a/plat/xilinx/zynqmp/
A Dplat_psci.c59 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_off()
83 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend()
85 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in zynqmp_pwr_domain_suspend()
92 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend()
102 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_on_finish()
114 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend_finish()
122 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend_finish()
171 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
173 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
184 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
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/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_pm.c106 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_power_domain_on_finish_common()
113 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_power_domain_on_finish_common()
130 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == in fvp_power_domain_on_finish_common()
202 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_off()
220 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_pwr_domain_off()
238 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend()
242 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend()
261 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_pwr_domain_suspend()
266 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == in fvp_pwr_domain_suspend()
311 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend_finish()
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/trusted-firmware-a/plat/imx/common/
A Dimx8_psci.c43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/trusted-firmware-a/plat/rockchip/common/
A Dplat_pm.c22 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
24 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
153 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()
157 req_state->pwr_domain_state[i] = in rockchip_validate_power_state()
161 req_state->pwr_domain_state[i] = in rockchip_validate_power_state()
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state()
232 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_off()
268 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_suspend()
289 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_on_finish()
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/trusted-firmware-a/plat/nvidia/tegra/soc/t210/
A Dplat_psci_handlers.c55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state()
65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()
82 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in tegra_soc_validate_power_state()
84 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = in tegra_soc_validate_power_state()
197 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_suspend() local
198 target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend()
199 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; in tegra_soc_pwr_domain_suspend()
344 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local
345 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi()
451 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_soc_pwr_domain_on_finish()
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/trusted-firmware-a/plat/qti/common/src/
A Dqti_pm.c105 req_state->pwr_domain_state[i++] = state_id & in qti_validate_power_state()
146 if ((target_state->pwr_domain_state[QTI_PWR_LVL0] == in is_cpu_off()
148 (target_state->pwr_domain_state[QTI_PWR_LVL0] == in is_cpu_off()
159 (const uint8_t *)target_state->pwr_domain_state; in qti_cpu_power_on_finish()
174 target_state->pwr_domain_state); in qti_node_power_off()
184 pwr_domain_state); in qti_node_suspend()
194 (const uint8_t *)target_state->pwr_domain_state; in qti_node_suspend_finish()
246 req_state->pwr_domain_state[i++] = in qti_get_sys_suspend_power_state()
/trusted-firmware-a/plat/allwinner/common/
A Dsunxi_scpi_pm.c41 ((state)->pwr_domain_state[CPU_PWR_LVL])
43 ((state)->pwr_domain_state[CLUSTER_PWR_LVL])
45 ((state)->pwr_domain_state[SYSTEM_PWR_LVL])
158 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in sunxi_validate_power_state()
166 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_validate_power_state()
171 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; in sunxi_validate_power_state()
182 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c81 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state()
82 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()
103 const plat_local_state_t *pwr_domain_state; in tegra_soc_pwr_domain_suspend() local
112 pwr_domain_state = target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend()
113 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & in tegra_soc_pwr_domain_suspend()
115 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_suspend()
281 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local
282 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi()
284 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_power_down_wfi()
372 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; in tegra_soc_pwr_domain_on_finish()
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/trusted-firmware-a/plat/mediatek/mt8173/
A Dplat_pm.c37 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
38 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
40 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
379 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) in plat_power_domain_on_finish()
382 if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { in plat_power_domain_on_finish()
388 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) in plat_power_domain_on_finish()
406 if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET) in plat_power_domain_suspend_finish()
439 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_get_sys_suspend_power_state()
490 req_state->pwr_domain_state[MTK_PWR_LVL0] = in plat_validate_power_state()
494 req_state->pwr_domain_state[i] = in plat_validate_power_state()
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/trusted-firmware-a/plat/intel/soc/common/
A Dsocfpga_psci.c62 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_off()
78 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend()
94 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_on_finish()
117 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend_finish()
192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
/trusted-firmware-a/plat/renesas/common/
A Dplat_pm.c35 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
36 #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
37 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
259 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
262 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
281 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
286 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state()
288 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in rcar_get_sys_suspend_power_state()
/trusted-firmware-a/plat/imx/imx8m/include/
A Dimx8m_psci.h10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
12 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
/trusted-firmware-a/plat/mediatek/mt8195/include/
A Dplat_pm.h28 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
30 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
32 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
/trusted-firmware-a/plat/mediatek/mt8192/include/
A Dplat_pm.h28 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
30 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
32 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_psci_handlers.c82 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in tegra_soc_validate_power_state()
83 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN; in tegra_soc_validate_power_state()
116 const plat_local_state_t *pwr_domain_state; in tegra_soc_pwr_domain_suspend() local
131 pwr_domain_state = target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend()
132 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_suspend()
265 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local
266 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi()
268 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_power_down_wfi()
348 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; in tegra_soc_pwr_domain_on_finish()
/trusted-firmware-a/plat/hisilicon/hikey/
A Dhikey_pm.c24 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
26 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
28 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
168 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey_get_sys_suspend_power_state()
235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()
239 req_state->pwr_domain_state[i] = in hikey_validate_power_state()
/trusted-firmware-a/include/plat/arm/css/common/
A Dcss_pm.h16 #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
17 #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
22 return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; in css_system_pwr_state()
/trusted-firmware-a/plat/mediatek/mt8183/
A Dplat_pm.c81 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
82 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
84 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
331 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_off()
350 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_on_finish()
366 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_suspend()
406 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_suspend_finish()
471 req_state->pwr_domain_state[i++] = state_id & in plat_mtk_validate_power_state()
502 req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET; in plat_mtk_validate_power_state()
507 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_mtk_validate_power_state()
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/trusted-firmware-a/plat/amlogic/axg/
A Daxg_pm.c102 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_on_finish()
117 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_off()
124 if (target_state->pwr_domain_state[MPIDR_AFFLVL2] == in axg_pwr_domain_off()
128 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in axg_pwr_domain_off()
/trusted-firmware-a/plat/hisilicon/hikey960/
A Dhikey960_pm.c27 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
29 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
31 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
159 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state()
163 req_state->pwr_domain_state[i] = in hikey960_validate_power_state()
294 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey960_get_sys_suspend_power_state()
/trusted-firmware-a/plat/imx/imx8qx/
A Dimx8qx_psci.c116 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) { in imx_domain_suspend()
127 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend()
130 if (is_local_state_retn(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL])) { in imx_domain_suspend()
169 if (is_local_state_retn(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL])) { in imx_domain_suspend_finish()
203 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend_finish()
206 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) { in imx_domain_suspend_finish()
/trusted-firmware-a/plat/hisilicon/poplar/
A Dplat_pm.c76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in poplar_pwr_domain_on_finish()
120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state()
122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
148 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in poplar_get_sys_suspend_power_state()
/trusted-firmware-a/lib/psci/
A Dpsci_common.c309 plat_local_state_t *pd_state = target_state->pwr_domain_state; in psci_get_target_local_pwr_states()
322 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; in psci_get_target_local_pwr_states()
335 const plat_local_state_t *pd_state = target_state->pwr_domain_state; in psci_set_target_local_pwr_states()
437 state_info->pwr_domain_state[lvl]); in psci_do_state_coordination()
452 state_info->pwr_domain_state[lvl] = target_state; in psci_do_state_coordination()
455 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) in psci_do_state_coordination()
469 state_info->pwr_domain_state[lvl]); in psci_do_state_coordination()
470 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; in psci_do_state_coordination()
506 state = state_info->pwr_domain_state[i]; in psci_validate_suspend_req()
551 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) in psci_find_max_off_lvl()
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