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/trusted-firmware-a/lib/extensions/mtpmu/aarch32/
A Dmtpmu.S31 mov r0, #0
32 addeq r0, r0, #1
44 cmp r0, #3
46 lsreq r0, r0, #ID_PFR1_SEC_SHIFT
47 lsrne r0, r0, #ID_PFR1_VIRTEXT_SHIFT
52 and r0, r0, #ID_PFR1_VIRTEXT_MASK
54 mov r0, #0
55 addeq r0, r0, #1
69 cmp r0, #0
81 bic r0, r0, r1
[all …]
/trusted-firmware-a/include/arch/aarch32/
A Del3_common_macros.S35 orr r0, r0, r1
47 stcopr r0, SCR
75 and r0, r0, #NSACR_IMP_DEF_MASK
76 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
81 orr r0, r0, #NSTRCDIS_BIT
148 orr r0, r0, #SDCR_TTRF_BIT
184 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT)
188 orr r0, r0, #CPSR_DIT_BIT
293 cmp r0, #0
294 bxne r0
[all …]
/trusted-firmware-a/lib/cpus/aarch32/
A Dcortex_a57.S46 mov r0, #1
53 mov r0, #0
407 mov r4, r0
410 mov r0, r4
415 mov r0, r4
420 mov r0, r4
425 mov r0, r4
430 mov r0, r4
435 mov r0, r4
440 mov r0, r4
[all …]
A Dcpu_helpers.S34 cmp r0, #0
64 cmp r0, r2
71 ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
73 cmp r0, #0
97 mov r6, r0
103 cmp r0, #0
130 mov r0, #0
154 cmp r0, #0
188 cmp r0, r1
226 ldr r0, [r0, #CPU_ERRATA_FUNC]
[all …]
A Dcortex_a72.S57 mov r0, #1
58 stcopr r0, DBGOSDLR
111 mov r4, r0
114 mov r0, r4
146 ldcopr r0, SCTLR
147 tst r0, #SCTLR_C_BIT
167 mov r0, #DC_OP_CISW
193 ldcopr r0, SCTLR
215 mov r0, #DC_OP_CISW
229 mov r0, #DC_OP_CISW
[all …]
A Dcortex_a17.S15 ldcopr r0, SCTLR
22 ldcopr r0, ACTLR
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
33 stcopr r0, ACTLR
55 orr r0, r0, #(1<<24)
83 orr r0, r0, #(1<<12)
111 mov r4, r0
129 mov r4, r0
132 mov r0, r4
[all …]
A Dcortex_a53.S43 mov r0, #ERRATA_APPLIES
187 mov r4, r0
190 mov r0, r4
195 mov r0, r4
200 mov r0, r4
224 ldcopr r0, SCTLR
233 mov r0, #DC_OP_CISW
254 ldcopr r0, SCTLR
263 mov r0, #DC_OP_CISW
276 mov r0, #DC_OP_CISW
[all …]
A Dcortex_a15.S21 ldcopr r0, SCTLR
28 ldcopr r0, ACTLR
30 stcopr r0, ACTLR
36 mov r0, #0
37 stcopr r0, TLBIMVA
44 ldcopr r0, ACTLR
46 stcopr r0, ACTLR
111 mov r4, r0
135 ldcopr r0, ACTLR
137 stcopr r0, ACTLR
[all …]
A Dcortex_a9.S15 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
22 ldcopr r0, ACTLR
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
33 stcopr r0, ACTLR
64 mov r4, r0
81 stcopr r0, VBAR
82 stcopr r0, MVBAR
94 mov r0, #DC_OP_CISW
[all …]
A Dcortex_a32.S20 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
21 bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
22 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
39 orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
56 ldcopr r0, SCTLR
57 tst r0, #SCTLR_C_BIT
65 mov r0, #DC_OP_CISW
87 ldcopr r0, SCTLR
88 tst r0, #SCTLR_C_BIT
96 mov r0, #DC_OP_CISW
[all …]
/trusted-firmware-a/drivers/arm/pl011/aarch32/
A Dpl011_console.S42 cmp r0, #0
58 push {r0,r3}
60 mov r2, r0
61 pop {r0,r3}
82 mov r0, #1
85 mov r0, #0
114 cmp r0, #0
117 mov r0, r4
190 cmp r0, #0
220 ldr r0, [r0, #CONSOLE_T_BASE]
[all …]
/trusted-firmware-a/plat/arm/css/common/aarch32/
A Dcss_helpers.S45 ldr r0, [r0]
59 and r0, r0, #MPIDR_CLUSTER_MASK
61 add r0, r1, r0, LSR #6
76 mov r4, r0
80 cmp r0, r1
82 cmp r0, r4
83 moveq r0, #1
84 movne r0, #0
97 cmp r0, r1
98 moveq r0, #1
[all …]
/trusted-firmware-a/plat/arm/board/a5ds/aarch32/
A Da5ds_helpers.S27 lsl r0, r0, #A5DS_HOLD_ENTRY_SHIFT
31 str r3, [r2, r0]
36 ldr r1, [r2, r0]
40 ldr r1, [r0]
57 mov r0, #0
72 and r0, r1
73 cmp r0, #0
74 moveq r0, #1
75 movne r0, #0
105 mov r3, r0
[all …]
/trusted-firmware-a/drivers/ti/uart/aarch32/
A D16550_console.S42 cmp r0, #0
82 mov r0, #1
85 mov r0, #0
121 cmp r0, #0
125 mov r0, r4
199 cmp r0, #0
208 mov r0, r1
227 cmp r0, #0
230 ldr r0, [r0, #CONSOLE_T_BASE]
245 cmp r0, #0
[all …]
/trusted-firmware-a/plat/qemu/common/aarch32/
A Dplat_helpers.S25 ldcopr r0, MPIDR
35 and r0, r0, #MPIDR_CLUSTER_MASK
36 add r0, r1, r0, LSR #6
48 ldcopr r0, MPIDR
50 and r0, r1
52 moveq r0, #1
53 movne r0, #0
69 lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
74 ldr r1, [r2, r0]
84 ldr r1, [r0]
[all …]
/trusted-firmware-a/bl32/sp_min/aarch32/
A Dentrypoint.S72 mov r9, r0
132 mov r0, r9
151 sub r1, r1, r0
156 sub r1, r1, r0
221 stcopr r0, SCR
231 mov r0, r2
270 pop {r0, r3}
333 mov r0, #0
350 mov r5, r0
353 mov r4, r0
[all …]
/trusted-firmware-a/lib/extensions/amu/aarch32/
A Damu_helpers.S26 mov r1, r0
37 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
38 add r1, r1, r0
61 mov r1, r0
72 lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
73 add r1, r1, r0
97 mov r1, r0
108 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
109 add r1, r1, r0
157 mov r1, r0
[all …]
/trusted-firmware-a/bl2/aarch32/
A Dbl2_entrypoint.S32 mov r9, r0
42 stcopr r0, VBAR
49 ldcopr r0, SCTLR
50 orr r0, r0, #SCTLR_I_BIT
51 bic r0, r0, #SCTLR_DSSBS_BIT
52 stcopr r0, SCTLR
71 ldr r0, =__RW_START__
73 sub r1, r1, r0
84 sub r1, r1, r0
90 sub r1, r1, r0
[all …]
/trusted-firmware-a/drivers/st/uart/aarch32/
A Dstm32_console.S46 cmp r0, #0
50 ldr r3, [r0, #USART_CR1]
87 mov r0, #1
90 mov r0, #0
119 cmp r0, #0
122 mov r0, r4
160 mov r0, #-1
196 mov r0, #-1
213 cmp r0, #0
235 cmp r0, #0
[all …]
/trusted-firmware-a/plat/arm/board/fvp/aarch32/
A Dfvp_helpers.S64 mov r0, #0
75 ldr r0, [r0]
76 cmp r0, #0
97 ldcopr r0, MPIDR
99 and r0, r1
100 cmp r0, #FVP_PRIMARY_CPU
101 moveq r0, #1
102 movne r0, #0
122 mov r3, r0
128 tst r0, #MPIDR_MT_MASK
[all …]
/trusted-firmware-a/plat/rockchip/common/aarch32/
A Dplat_helpers.S38 ldcopr r0, MPIDR
39 and r1, r0, #MPIDR_CPU_MASK
41 and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
43 and r0, r0, #MPIDR_CLUSTER_MASK
45 add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
65 ldcopr r0, MPIDR
71 and r0, r1
73 moveq r0, #1
74 movne r0, #0
97 ldcopr r0, MPIDR
[all …]
/trusted-firmware-a/bl2u/aarch32/
A Dbl2u_entrypoint.S40 ldr r0, =bl2u_vector_table
41 stcopr r0, VBAR
48 ldcopr r0, SCTLR
49 orr r0, r0, #SCTLR_I_BIT
50 bic r0, r0, #SCTLR_DSSBS_BIT
51 stcopr r0, SCTLR
70 ldr r0, =__RW_START__
72 sub r1, r1, r0
81 ldr r0, =__BSS_START__
83 sub r1, r1, r0
[all …]
/trusted-firmware-a/plat/arm/board/juno/aarch32/
A Djuno_helpers.S31 cmp r0, #\_revision
54 mov r0, #(0xf << EVNTI_SHIFT)
55 orr r0, r0, #EVNTEN_BIT
56 stcopr r0, CNTKCTL
70 stcopr r0, CORTEX_A57_L2CTLR
105 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
106 stcopr r0, CORTEX_A57_L2CTLR
141 stcopr r0, CORTEX_A72_L2CTLR
155 ldr r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID)
156 ldr r1, [r0]
[all …]
/trusted-firmware-a/common/aarch32/
A Ddebug.S50 add r0, r0, #ASCII_OFFSET_NUM /* Convert to ascii */
74 mov r5, r0
81 cmp r0, #0
122 cmp r0, #0
143 lsr r0, r4, r5
144 and r0, r0, #0xf
145 cmp r0, #0xa
150 add r0, r0, #0x27
152 add r0, r0, #ASCII_OFFSET_NUM
175 cmp r0, #0
[all …]
/trusted-firmware-a/lib/psci/aarch32/
A Dpsci_helpers.S40 mov r4, r0
48 mov r0, r4
81 sub r1, r0, r1
82 mov r0, sp
89 ldcopr r0, SCTLR
90 orr r0, r0, #SCTLR_C_BIT
91 stcopr r0, SCTLR
119 mov r4, r0
121 sub r1, r0, r1
122 mov r0, sp
[all …]

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