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Searched refs:r1 (Results 1 – 25 of 73) sorted by relevance

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/trusted-firmware-a/lib/extensions/amu/aarch32/
A Damu_helpers.S27 lsr r1, r1, #2
38 add r1, r1, r0
39 bx r1
62 lsr r1, r1, #2
73 add r1, r1, r0
74 bx r1
98 lsr r1, r1, #4
109 add r1, r1, r0
110 bx r1
158 lsr r1, r1, #4
[all …]
/trusted-firmware-a/lib/xlat_tables_v2/aarch32/
A Denable_mmu.S18 ldcopr r1, SCTLR
19 tst r1, #SCTLR_M_BIT
31 stcopr r1, MAIR0
43 mov r1, #0
56 ldcopr r1, SCTLR
58 orr r1, r1, r2
62 bicne r1, r1, #SCTLR_C_BIT
64 stcopr r1, SCTLR
88 stcopr r1, HMAIR0
110 orr r1, r1, r2
[all …]
/trusted-firmware-a/lib/libc/aarch32/
A Dmemset.S29 strbhs r1, [r12], #1
35 aligned:bfi r1, r1, #8, #8 /* propagate 'val' */
36 bfi r1, r1, #16, #16
38 mov r3, r1
44 mov r4, r1
45 mov lr, r1
49 stmiahs r12!, {r1, r3, r4, lr}
50 stmiahs r12!, {r1, r3, r4, lr}
58 strcs r1, [r12], #4 /* write 4 bytes */
62 strbmi r1, [r12] /* write 1 byte */
[all …]
/trusted-firmware-a/drivers/arm/pl011/aarch32/
A Dpl011_console.S46 cmp r1, #0
56 lsl r1, r1, #2
59 softudiv r0,r1,r2,r3
63 udiv r2, r1, r2
66 lsr r1, r2, #6
70 and r1, r2, #0x3f
76 mov r1, #0
137 cmp r1, #0
173 cmp r1, #0
176 ldr r1, [r1, #CONSOLE_T_BASE]
[all …]
/trusted-firmware-a/lib/cpus/aarch32/
A Dcortex_a57.S85 mov r1, #0x00
129 mov r1, #0x00
158 mov r1, #0x00
204 mov r1, #0x12
233 mov r1, #0x11
262 mov r1, #0x11
297 mov r1, #0x11
326 mov r1, #0x12
348 orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
355 mov r1, #0x12
[all …]
A Dcpu_helpers.S40 cmp r1, #0
42 bxne r1
79 add r1, r1, r2, lsl #2
80 ldr r1, [r0, r1]
82 cmp r1, #0
85 bx r1
99 cmp r1, #0
145 and r1, r1, r3
148 cmp r1, r2
188 cmp r0, r1
[all …]
A Dcortex_a72.S18 ldcopr16 r0, r1, CORTEX_A72_ECTLR
22 stcopr16 r0, r1, CORTEX_A72_ECTLR
32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
46 ldcopr16 r0, r1, CORTEX_A72_ECTLR
48 stcopr16 r0, r1, CORTEX_A72_ECTLR
78 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
79 orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH
86 mov r1, #0x03
130 ldcopr16 r0, r1, CORTEX_A72_ECTLR
[all …]
A Dcortex_a53.S24 ldcopr16 r0, r1, CORTEX_A53_ECTLR
26 stcopr16 r0, r1, CORTEX_A53_ECTLR
88 mov r1, #0x02
133 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
135 stcopr16 r0, r1, CORTEX_A53_CPUACTLR
141 mov r1, #0x03
167 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
169 stcopr16 r0, r1, CORTEX_A53_CPUACTLR
175 mov r1, #0x03
208 ldcopr16 r0, r1, CORTEX_A53_ECTLR
[all …]
/trusted-firmware-a/lib/aarch32/
A Dmisc_helpers.S147 orr r3, r0, r1
183 bic r0, r0, r1
219 mov r7, r1
225 tst r0, r1
239 add r1, r1, r0
259 str r3, [r1]
261 2: add r1, r1, #4
262 cmp r1, r2
267 add r1, r1, r0
311 2: add r1, r1, #8
[all …]
A Dcache_helpers.S24 cmp r1, #0
27 add r1, r0, r1
33 cmp r0, r1
88 mov r1, #0
97 add r10, r1, r1, LSR #1 // Work out 3x current cache level
103 stcopr r1, CSSELR // select current cache level in csselr
116 orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
125 add r1, r1, #2 // increment the cache number
126 cmp r3, r1
181 sub r1, r3, #2
/trusted-firmware-a/plat/st/stm32mp1/
A Dstm32mp1_helper.S115 and r0, r1
129 and r1, r0, #MPIDR_CPU_MASK
131 add r0, r1, r0, LSR #6
154 str r2, [r1]
156 ldr r0, [r1]
161 ldr r0, [r1]
166 ldr r2, [r1]
169 str r2, [r1]
201 str r2, [r1]
203 ldr r2, [r1]
[all …]
/trusted-firmware-a/include/arch/aarch32/
A Dconsole_macros.S26 ldr r1, =console_\_driver\()_putc
28 mov r1, #0
30 str r1, [r0, #CONSOLE_T_PUTC]
33 ldr r1, =console_\_driver\()_getc
35 mov r1, #0
37 str r1, [r0, #CONSOLE_T_GETC]
40 ldr r1, =console_\_driver\()_flush
42 mov r1, #0
44 str r1, [r0, #CONSOLE_T_FLUSH]
46 mov r1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
[all …]
A Del3_common_macros.S35 orr r0, r0, r1
77 ldcopr r1, ID_DFR0
78 ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH
144 ldcopr r1, ID_DFR0
145 ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH
311 and r0, r0, r1
313 add r1, r1, r0
398 ldr r1, =__RW_END__
399 sub r1, r1, r0
410 sub r1, r1, r0
[all …]
A Dsmccc_macros.S136 stcopr r1, SCR
142 tst r1, #SCR_NS_BIT
154 ldcopr r1, SDCR
162 stcopr r1, PMCR
175 ldm r1!, {sp, lr}
178 ldm r1!, {r2, sp, lr}
182 ldm r1!, {r2, sp, lr}
186 ldm r1!, {r2, sp, lr}
198 ldm r1!, {r2}
204 ldm r1!, {r4-r12}
[all …]
/trusted-firmware-a/drivers/ti/uart/aarch32/
A D16550_console.S45 cmp r1, #0
53 udiv r2, r1, r2
117 cmp r1, #0
145 cmp r1, #0
158 str r2, [r1, #UARTTX]
165 str r0, [r1, #UARTTX]
181 cmp r1, #0
184 ldr r1, [r1, #CONSOLE_T_BASE]
207 ldr r1, [r0, #UARTRX]
208 mov r0, r1
[all …]
/trusted-firmware-a/bl2/aarch32/
A Dbl2_entrypoint.S33 mov r10, r1
72 ldr r1, =__RW_END__
73 sub r1, r1, r0
83 ldr r1, =__BSS_END__
84 sub r1, r1, r0
89 ldr r1, =__COHERENT_RAM_END_UNALIGNED__
90 sub r1, r1, r0
118 mov r1, r10
/trusted-firmware-a/plat/qemu/common/aarch32/
A Dplat_helpers.S34 and r1, r0, #MPIDR_CPU_MASK
36 add r0, r1, r0, LSR #6
49 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
50 and r0, r1
74 ldr r1, [r2, r0]
79 mov r1, #PLAT_QEMU_HOLD_STATE_WAIT
80 str r1, [r2, r0]
84 ldr r1, [r0]
85 bx r1
110 mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
[all …]
/trusted-firmware-a/plat/arm/css/common/aarch32/
A Dcss_helpers.S58 and r1, r0, #MPIDR_CPU_MASK
61 add r0, r1, r0, LSR #6
79 mov r1, #0xffffffff
80 cmp r0, r1
93 ldr r1, =SCP_BOOT_CFG_ADDR
94 ldr r1, [r1]
95 ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
97 cmp r0, r1
/trusted-firmware-a/lib/psci/aarch32/
A Dpsci_helpers.S80 mov r1, sp
81 sub r1, r0, r1
109 ldcopr r1, SCTLR
110 bic r1, #SCTLR_C_BIT
111 stcopr r1, SCTLR
120 mov r1, sp
121 sub r1, r0, r1
132 sub r1, sp, r0
/trusted-firmware-a/plat/arm/board/a5ds/aarch32/
A Da5ds_helpers.S36 ldr r1, [r2, r0]
37 cmp r1, #A5DS_HOLD_STATE_WAIT
40 ldr r1, [r0]
41 bx r1
71 ldr r1, =MPIDR_AFFINITY_MASK
72 and r0, r1
116 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
121 mla r1, r2, r3, r1
123 mla r0, r1, r3, r0
/trusted-firmware-a/bl2u/aarch32/
A Dbl2u_entrypoint.S33 mov r11, r1
71 ldr r1, =__RW_END__
72 sub r1, r1, r0
82 ldr r1, =__BSS_END__
83 sub r1, r1, r0
111 mov r1, r10
/trusted-firmware-a/bl32/sp_min/aarch32/
A Dentrypoint.S73 mov r10, r1
133 mov r1, r10
150 ldr r1, =__DATA_END__
151 sub r1, r1, r0
155 ldr r1, =__BSS_END__
156 sub r1, r1, r0
181 ldcopr16 r0, r1, CNTPCT_64
183 strd r0, r1, [lr, #-8]!
235 mov r1, #0 /* cookie */
361 mov r1, #PMF_TS_SIZE
[all …]
/trusted-firmware-a/lib/locks/exclusive/aarch32/
A Dspinlock.S27 ldrex r1, [r0]
28 cmp r1, #0
30 strexeq r1, r2, [r0]
31 cmpeq r1, #0
39 mov r1, #0
40 stl r1, [r0]
/trusted-firmware-a/plat/arm/board/fvp/aarch32/
A Dfvp_helpers.S54 ldr r1, =PWRC_BASE
55 str r2, [r1, #PSYSR_OFF]
56 ldr r2, [r1, #PSYSR_OFF]
98 ldr r1, =MPIDR_AFFINITY_MASK
99 and r0, r1
133 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
138 mla r1, r2, r3, r1
140 mla r0, r1, r3, r0
/trusted-firmware-a/plat/rockchip/common/aarch32/
A Dplat_helpers.S39 and r1, r0, #MPIDR_CPU_MASK
45 add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
67 ldr r1, =(PLAT_RK_MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
69 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
71 and r0, r1
119 ldr r1, [r4]
124 cmp r1, #PMU_CPU_AUTO_PWRDN
126 cmp r1, #PMU_CPU_HOTPLUG
137 mov r1, #0
138 str r1, [r4]

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