| /trusted-firmware-a/common/aarch32/ |
| A D | debug.S | 46 ldr r5, =MAX_DEC_DIVISOR
48 udiv r0, r4, r5 /* Get the quotient */
49 mls r4, r0, r5, r4 /* Find the remainder */
52 udiv r5, r5, r6 /* Reduce divisor */
53 cmp r5, #0
74 mov r5, r0
87 mov r4, r5
136 mov r5, #32 /* No of bits to convert to ascii */
142 sub r5, r5, #4
143 lsr r0, r4, r5
[all …]
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| /trusted-firmware-a/plat/allwinner/common/ |
| A D | arisc_off.S | 60 l.lwz r5, 0x1500(r13) # core output clamps
61 l.or r5, r5, r6 # set bit to ...
62 l.sw 0x1500(r13), r5 # ... activate for our core
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
66 l.and r5, r5, r6 # clear bit to ...
67 l.sw 0x1c30(r13), r5 # ... assert for our core
71 l.slli r6, r6, 2 # r5: core number*4 (0-12)
73 l.ori r5, r0, 0xff # 0xff means all switches off
87 l.lwz r5, 0x80(r13) # load C_CPU_STATUS
88 l.and r5, r5, r3 # mask requested core
[all …]
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| /trusted-firmware-a/include/arch/aarch32/ |
| A D | smccc_macros.S | 64 mrs r5, lr_usr
75 mrs r5, lr_svc
95 ldcopr r5, SDCR
96 tst r5, #SDCR_SCCD_BIT
101 ldcopr r5, PMCR
108 str r5, [sp, #SMC_CTX_PMCR]
111 2: orr r5, r5, #PMCR_DP_BIT
112 stcopr r5, PMCR
206 msr lr_usr, r5
217 msr lr_svc, r5
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| A D | smccc_helpers.h | 44 u_register_t r5; member
138 ((smc_ctx_t *)(_h))->r5 = (_r5); \
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| A D | arch_helpers.h | 209 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
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| /trusted-firmware-a/plat/rockchip/common/aarch32/ |
| A D | plat_helpers.S | 98 and r5, r0, #MPIDR_CPU_MASK
112 add r7, r5, r6, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
143 ldr r5, =cpuson_entry_point
144 ldr r2, [r5, r7, lsl #2] /* ehem. #3 */
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| /trusted-firmware-a/drivers/renesas/common/ddr/ddr_a/ |
| A D | ddr_init_d3.c | 26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
186 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr_d3_1866()
212 ((r6 + (r5 << 1)) & 0xFF)); in init_ddr_d3_1866()
265 r12 = (r5 >> 0x2); in init_ddr_d3_1866()
287 ((r6 + r5 + in init_ddr_d3_1866()
288 (r5 >> 1) + r12) & 0xFF)); in init_ddr_d3_1866()
361 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1600() local
558 ((r6 + (r5 << 1)) & 0xFF)); in init_ddr_d3_1600()
611 r12 = (r5 >> 0x2); in init_ddr_d3_1600()
633 ((r6 + r5 + in init_ddr_d3_1600()
[all …]
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| A D | ddr_init_v3m.c | 17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
195 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; in init_ddr_v3m_1600()
221 (((r5 << 1) + r6) & 0xFF)); in init_ddr_v3m_1600()
267 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; in init_ddr_v3m_1600()
273 r12 = (r5 >> 2); in init_ddr_v3m_1600()
294 ((r6 + r5 + in init_ddr_v3m_1600()
295 (r5 >> 1) + r12) & 0xFF)); in init_ddr_v3m_1600()
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| A D | ddr_init_e3.c | 37 uint32_t i, r2, r5, r6, r7, r12; in init_ddr() local
378 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr()
402 ((r6 + ((r5) << 1)) & in init_ddr()
576 r12 = (r5 >> 0x2); in init_ddr()
594 mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + in init_ddr()
595 (r5 >> 1) + r12) & 0xFF)); in init_ddr()
839 uint32_t r2, r5, r6, r7, r12, i; in recovery_from_backup_mode() local
1250 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in recovery_from_backup_mode()
1274 r2 | ((r6 + (r5 << 1)) & 0xFF)); in recovery_from_backup_mode()
1429 r12 = r5 >> 0x2; in recovery_from_backup_mode()
[all …]
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| /trusted-firmware-a/bl1/aarch32/ |
| A D | bl1_entrypoint.S | 80 ldr r5, [r4, #SMC_CTX_SCR]
81 tst r5, #SCR_NS_BIT
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| A D | bl1_exceptions.S | 140 ldr r5, [r4, #SMC_CTX_SCR]
141 tst r5, #SCR_NS_BIT
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| /trusted-firmware-a/lib/cpus/aarch32/ |
| A D | cpu_helpers.S | 127 ldr r5, =(__CPU_OPS_END__ + CPU_MIDR)
140 cmp r4, r5
219 push {r4, r5, r12, lr}
262 pop {r4, r5, r12, pc}
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| A D | cortex_a15.S | 127 mov r5, lr
144 mov lr, r5
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| A D | cortex_a17.S | 127 mov r5, lr
148 mov lr, r5
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| A D | cortex_a72.S | 109 mov r5, lr
134 bx r5
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| A D | cortex_a53.S | 185 mov r5, lr
212 bx r5
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| A D | cortex_a57.S | 405 mov r5, lr
475 bx r5
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| /trusted-firmware-a/bl32/sp_min/aarch32/ |
| A D | entrypoint.S | 208 ldrd r4, r5, [sp], #8
210 strd r4, r5, [r0, #CPU_DATA_PMF_TS0_OFFSET]
350 mov r5, r0
368 mov r0, r5
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| /trusted-firmware-a/lib/aarch32/ |
| A D | cache_helpers.S | 109 clz r5, r4 // r5 = the bit position of the way size increment
116 orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
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| A D | misc_helpers.S | 30 ldm sp, {r4, r5, r6}
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| /trusted-firmware-a/services/spd/trusty/ |
| A D | trusty.c | 66 uint64_t r5; member
108 args.r5 = 0; in trusty_context_switch()
260 ret.r4, ret.r5, ret.r6, ret.r7); in trusty_smc_handler()
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| /trusted-firmware-a/include/drivers/brcm/emmc/ |
| A D | emmc_csl_sdcmd.h | 88 struct sd_r5_resp r5; member
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | rt-svc-writers-guide.rst.txt | 273 SMC_RET6(handle, r0, r1, r2, r3, r4, r5);
274 SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6);
275 SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7);
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| /trusted-firmware-a/docs/getting_started/ |
| A D | rt-svc-writers-guide.rst | 273 SMC_RET6(handle, r0, r1, r2, r3, r4, r5);
274 SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6);
275 SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7);
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| /trusted-firmware-a/drivers/brcm/emmc/ |
| A D | emmc_csl_sdcard.c | 886 resp->data.r5.data = rsp0 & 0xff; in process_cmd_response()
893 resp->data.r5.data = rsp0 & 0xff; in process_cmd_response()
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