| /trusted-firmware-a/plat/qti/qtiseclib/src/ |
| A D | qtiseclib_cb_interface.c | 141 read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); in qtiseclib_cb_get_ns_ctx()
145 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SPSR_EL1); in qtiseclib_cb_get_ns_ctx()
147 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_ELR_EL1); in qtiseclib_cb_get_ns_ctx()
150 qti_ns_ctx->x0 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0); in qtiseclib_cb_get_ns_ctx()
151 qti_ns_ctx->x1 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1); in qtiseclib_cb_get_ns_ctx()
152 qti_ns_ctx->x2 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2); in qtiseclib_cb_get_ns_ctx()
153 qti_ns_ctx->x3 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3); in qtiseclib_cb_get_ns_ctx()
154 qti_ns_ctx->x4 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4); in qtiseclib_cb_get_ns_ctx()
155 qti_ns_ctx->x5 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5); in qtiseclib_cb_get_ns_ctx()
156 qti_ns_ctx->x6 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6); in qtiseclib_cb_get_ns_ctx()
[all …]
|
| /trusted-firmware-a/bl1/aarch32/ |
| A D | bl1_context_mgmt.c | 74 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); in copy_cpu_ctx_to_smc_ctx()
75 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); in copy_cpu_ctx_to_smc_ctx()
76 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); in copy_cpu_ctx_to_smc_ctx()
77 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); in copy_cpu_ctx_to_smc_ctx()
78 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); in copy_cpu_ctx_to_smc_ctx()
79 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); in copy_cpu_ctx_to_smc_ctx()
80 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_ctx()
154 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in bl1_prepare_next_image()
|
| /trusted-firmware-a/bl32/sp_min/ |
| A D | sp_min_main.c | 112 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); in copy_cpu_ctx_to_smc_stx()
113 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); in copy_cpu_ctx_to_smc_stx()
114 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); in copy_cpu_ctx_to_smc_stx()
115 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); in copy_cpu_ctx_to_smc_stx()
116 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); in copy_cpu_ctx_to_smc_stx()
117 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_stx()
148 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in sp_min_prepare_next_image_entry()
227 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in sp_min_warm_boot()
|
| /trusted-firmware-a/include/arch/aarch64/ |
| A D | smccc_helpers.h | 60 read_ctx_reg((get_gpregs_ctx(_h)), (_g))
69 read_ctx_reg((get_el3state_ctx(_h)), (_e))
79 _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \
80 _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
81 _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \
82 _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
|
| /trusted-firmware-a/lib/extensions/sme/ |
| A D | sme.c | 47 reg = read_ctx_reg(state, CTX_CPTR_EL3); in sme_enable()
52 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_enable()
93 reg = read_ctx_reg(state, CTX_CPTR_EL3); in sme_disable()
100 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_disable()
|
| /trusted-firmware-a/plat/nvidia/tegra/common/ |
| A D | tegra_fiq_glue.c | 66 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler()
67 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); in tegra_fiq_interrupt_handler()
142 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); in tegra_fiq_get_intr_context()
145 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); in tegra_fiq_get_intr_context()
|
| /trusted-firmware-a/lib/extensions/sve/ |
| A D | sve.c | 36 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); in sve_enable()
61 reg = read_ctx_reg(state, CTX_CPTR_EL3); in sve_disable()
|
| /trusted-firmware-a/services/spd/opteed/ |
| A D | opteed_main.c | 251 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
255 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
259 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
264 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
|
| /trusted-firmware-a/plat/rockchip/rk3399/ |
| A D | plat_sip_calls.c | 70 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in rockchip_plat_sip_handler()
71 x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6); in rockchip_plat_sip_handler()
|
| /trusted-firmware-a/plat/arm/common/aarch64/ |
| A D | execution_state_switch.c | 61 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); in arm_execution_state_switch()
95 scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3); in arm_execution_state_switch()
|
| /trusted-firmware-a/lib/extensions/sys_reg_trace/aarch64/ |
| A D | sys_reg_trace.c | 33 val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); in sys_reg_trace_enable()
|
| /trusted-firmware-a/lib/el3_runtime/aarch32/ |
| A D | context_mgmt.c | 194 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); in cm_prepare_el3_exit()
197 hsctlr = read_ctx_reg(get_regs_ctx(ctx), in cm_prepare_el3_exit()
|
| /trusted-firmware-a/lib/el3_runtime/aarch64/ |
| A D | context_mgmt.c | 488 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), in cm_prepare_el3_exit()
492 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), in cm_prepare_el3_exit()
842 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); in cm_write_scr_el3_bit()
862 return read_ctx_reg(state, CTX_SCR_EL3); in cm_get_scr_el3()
|
| /trusted-firmware-a/include/lib/el3_runtime/aarch32/ |
| A D | context.h | 50 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[offset >> WORD_SHIFT]) macro
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| A D | mce.c | 186 arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); in mce_command_handler()
187 arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); in mce_command_handler()
188 arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); in mce_command_handler()
|
| /trusted-firmware-a/services/std_svc/spmd/ |
| A D | spmd_pm.c | 148 u_register_t ffa_resp_func = read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), in spmd_cpu_off_handler()
|
| /trusted-firmware-a/services/spd/trusty/ |
| A D | trusty.c | 163 ctx->fiq_sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1); in trusty_fiq_handler()
192 uint64_t sp_el0 = read_ctx_reg(&ctx->fiq_gpregs, CTX_GPREG_SP_EL0); in trusty_get_fiq_regs()
313 uint64_t reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx), in trusty_init()
|
| /trusted-firmware-a/services/std_svc/sdei/ |
| A D | sdei_intr_mgmt.c | 175 disp_ctx->spsr_el3 = read_ctx_reg(tgt_el3, CTX_SPSR_EL3); in save_event_ctx()
176 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx()
341 disp_ctx->disable_cve_2018_3639 = read_ctx_reg(tgt_cve_2018_3639, in setup_ns_dispatch()
|
| A D | sdei_private.h | 169 return ((read_ctx_reg(el3_ctx, CTX_SCR_EL3) & SCR_HCE_BIT) != 0U) ? in sdei_client_el()
|
| /trusted-firmware-a/services/std_svc/spm_mm/ |
| A D | spm_mm_setup.c | 134 u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1); in spm_sp_setup()
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
| A D | plat_psci_handlers.c | 359 actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1)); in tegra_soc_pwr_domain_on_finish()
|
| /trusted-firmware-a/plat/qti/common/src/ |
| A D | qti_syscall.c | 178 u_register_t x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in qti_sip_mem_assign()
|
| /trusted-firmware-a/lib/extensions/amu/aarch64/ |
| A D | amu.c | 80 uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); in write_cptr_el3_tam()
|
| /trusted-firmware-a/include/lib/el3_runtime/aarch64/ |
| A D | context.h | 403 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) macro
|