Searched refs:reg_id (Results 1 – 4 of 4) sorted by relevance
225 enum sw_reg reg_id; in dump_swreg_firmware() local230 for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) { in dump_swreg_firmware()258 if (reg_id == DDR_VDDC) in set_swreg()268 if (reg_id == DDR_VDDC) in set_swreg()302 enum sw_reg reg_id; in swreg_firmware_update() local308 for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) { in swreg_firmware_update()319 for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) { in swreg_firmware_update()324 if ((reg_id == DDRIO_SLAVE) || (reg_id == VDDC1)) in swreg_firmware_update()335 for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) { in swreg_firmware_update()341 if (reg_id == IHOST_ARRAY) in swreg_firmware_update()[all …]
50 int reg_id = 0; in tzc380_setup() local65 for (reg_id = 0; reg_id < MAX_NUM_TZC_REGION; reg_id++) { in tzc380_setup()67 reg_id, in tzc380_setup()68 tzc380_reg_list[reg_id].enabled, in tzc380_setup()69 tzc380_reg_list[reg_id].low_addr, in tzc380_setup()70 tzc380_reg_list[reg_id].high_addr, in tzc380_setup()71 tzc380_reg_list[reg_id].size, in tzc380_setup()72 tzc380_reg_list[reg_id].secure, in tzc380_setup()73 tzc380_reg_list[reg_id].sub_mask); in tzc380_setup()
40 uint8_t reg_id = 0U; in populate_dram_regions_info() local42 dram_regions_info.region[reg_id].addr = NXP_DRAM0_ADDR; in populate_dram_regions_info()43 dram_regions_info.region[reg_id].size = in populate_dram_regions_info()55 assert(dram_regions_info.region[reg_id].size > 0); in populate_dram_regions_info()63 reg_id++; in populate_dram_regions_info()64 dram_regions_info.region[reg_id].addr = NXP_DRAM1_ADDR; in populate_dram_regions_info()65 dram_regions_info.region[reg_id].size = in populate_dram_regions_info()73 reg_id++; in populate_dram_regions_info()75 dram_regions_info.region[reg_id].size = in populate_dram_regions_info()81 reg_id++; in populate_dram_regions_info()[all …]
33 int set_swreg(enum sw_reg reg_id, uint32_t micro_volts);
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