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Searched refs:reg_val (Results 1 – 13 of 13) sorted by relevance

/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_pm.c121 uint32_t reg_val; in plat_marvell_cpu_powerdown() local
140 reg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK; in plat_marvell_cpu_powerdown()
155 reg_val &= ~PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK; in plat_marvell_cpu_powerdown()
159 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); in plat_marvell_cpu_powerdown()
160 reg_val &= ~CCU_B_PRCRN_CPUPORESET_STATIC_MASK; in plat_marvell_cpu_powerdown()
161 mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
229 uint32_t reg_val; in plat_marvell_cpu_powerup() local
241 reg_val = mmio_read_32(AP807_PWRC_LDO_CR0_REG); in plat_marvell_cpu_powerup()
242 reg_val &= ~(AP807_PWRC_LDO_CR0_MASK); in plat_marvell_cpu_powerup()
244 mmio_write_32(AP807_PWRC_LDO_CR0_REG, reg_val); in plat_marvell_cpu_powerup()
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A Dplat_ble_setup.c360 uint32_t reg_val, avs_workpoint, freq_pidi_mode; in ble_plat_svc_config() local
373 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); in ble_plat_svc_config()
374 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; in ble_plat_svc_config()
375 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); in ble_plat_svc_config()
531 reg_val = mmio_read_32(AVS_EN_CTRL_REG); in ble_plat_svc_config()
532 avs_workpoint = (reg_val & in ble_plat_svc_config()
612 reg_val = mmio_read_32(AVS_EN_CTRL_REG); in ble_plat_svc_config()
617 reg_val |= 0x1 << AVS_ENABLE_OFFSET; in ble_plat_svc_config()
618 reg_val |= avs_workpoint << AVS_HIGH_VDD_LIMIT_OFFSET; in ble_plat_svc_config()
619 reg_val |= avs_workpoint << AVS_LOW_VDD_LIMIT_OFFSET; in ble_plat_svc_config()
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/trusted-firmware-a/drivers/arm/gic/v3/
A Dgic600ae_fmu_helpers.c100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U); in gic_fmu_read_errfr() local
102 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32); in gic_fmu_read_errfr()
103 return reg_val; in gic_fmu_read_errfr()
119 return reg_val; in gic_fmu_read_errctlr()
135 return reg_val; in gic_fmu_read_errstatus()
147 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRGSR_LO); in gic_fmu_read_errgsr() local
149 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRGSR_HI) << 32); in gic_fmu_read_errgsr()
150 return reg_val; in gic_fmu_read_errgsr()
178 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_PINGMASK_LO); in gic_fmu_read_pingmask() local
180 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_PINGMASK_HI) << 32); in gic_fmu_read_pingmask()
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/trusted-firmware-a/drivers/arm/smmu/
A Dsmmu_v3.c19 uint32_t reg_val; in smmuv3_poll() local
25 reg_val = mmio_read_32(smmu_reg); in smmuv3_poll()
26 if ((reg_val & mask) == value) in smmuv3_poll()
31 ERROR("Read value 0x%x, expected 0x%x\n", reg_val, in smmuv3_poll()
32 value == 0U ? reg_val & ~mask : reg_val | mask); in smmuv3_poll()
/trusted-firmware-a/drivers/nxp/timer/
A Dnxp_timer.c122 unsigned int reg_val; in ls_configure_sys_timer() local
125 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); in ls_configure_sys_timer()
126 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); in ls_configure_sys_timer()
127 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); in ls_configure_sys_timer()
129 CNTACR_BASE(plat_ls_ns_timer_frame_id), reg_val); in ls_configure_sys_timer()
133 reg_val = (1U << CNTNSAR_NS_SHIFT(plat_ls_ns_timer_frame_id)); in ls_configure_sys_timer()
134 mmio_write_32(ls_sys_timctl_base + CNTNSAR, reg_val); in ls_configure_sys_timer()
/trusted-firmware-a/drivers/nxp/crypto/caam/src/
A Dsec_hw_specific.c328 uint32_t reg_val = 0U; in hw_job_ring_set_coalescing_param() local
339 sec_out32(&regs->jrcfg1, reg_val); in hw_job_ring_set_coalescing_param()
348 uint32_t reg_val = 0U; in hw_job_ring_enable_coalescing() local
353 reg_val = sec_in32(&regs->jrcfg1); in hw_job_ring_enable_coalescing()
359 sec_out32(&regs->jrcfg1, reg_val); in hw_job_ring_enable_coalescing()
368 uint32_t reg_val = 0U; in hw_job_ring_disable_coalescing() local
373 reg_val = sec_in32(&regs->jrcfg1); in hw_job_ring_disable_coalescing()
379 sec_out32(&regs->jrcfg1, reg_val); in hw_job_ring_disable_coalescing()
599 uint32_t reg_val = 0U; in jr_enable_irqs() local
604 reg_val = sec_in32(&regs->jrcfg1); in jr_enable_irqs()
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/trusted-firmware-a/plat/arm/common/
A Darm_common.c132 unsigned int reg_val; in arm_configure_sys_timer() local
138 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT); in arm_configure_sys_timer()
139 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT); in arm_configure_sys_timer()
140 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT); in arm_configure_sys_timer()
141 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); in arm_configure_sys_timer()
144 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); in arm_configure_sys_timer()
145 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); in arm_configure_sys_timer()
/trusted-firmware-a/drivers/arm/gic/common/
A Dgic_common.c251 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_get_igroupr() local
253 return (reg_val >> bit_num) & 0x1U; in gicd_get_igroupr()
259 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_set_igroupr() local
261 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); in gicd_set_igroupr()
267 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_clr_igroupr() local
303 unsigned int reg_val = gicd_read_isactiver(base, id); in gicd_get_isactiver() local
305 return (reg_val >> bit_num) & 0x1U; in gicd_get_isactiver()
335 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr() local
338 reg_val &= ~(GIC_CFG_MASK << bit_shift); in gicd_set_icfgr()
339 reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); in gicd_set_icfgr()
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/trusted-firmware-a/drivers/arm/gic/v2/
A Dgicdv2_helpers.c249 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_get_igroupr() local
251 return (reg_val >> bit_num) & 0x1U; in gicd_get_igroupr()
257 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_set_igroupr() local
259 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); in gicd_set_igroupr()
265 unsigned int reg_val = gicd_read_igroupr(base, id); in gicd_clr_igroupr() local
301 unsigned int reg_val = gicd_read_isactiver(base, id); in gicd_get_isactiver() local
303 return (reg_val >> bit_num) & 0x1U; in gicd_get_isactiver()
333 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr() local
336 reg_val &= ~(GIC_CFG_MASK << bit_shift); in gicd_set_icfgr()
337 reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); in gicd_set_icfgr()
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/trusted-firmware-a/drivers/brcm/emmc/
A Demmc_chal_sd.c194 uint32_t reg_val; in chal_sd_init() local
207 reg_val = 0; in chal_sd_init()
209 reg_val |= (0 << ICFG_SDIO0_CAP0__INT_MODE_R); in chal_sd_init()
215 reg_val |= (1 << ICFG_SDIO0_CAP0__SDMA_R); in chal_sd_init()
217 reg_val |= (1 << ICFG_SDIO0_CAP0__ADMA2_R); in chal_sd_init()
224 mmio_write_32(ICFG_SDIO0_CAP0, reg_val); in chal_sd_init()
226 reg_val = 0; in chal_sd_init()
236 reg_val |= (1 << ICFG_SDIO0_CAP1__DDR50_R); in chal_sd_init()
237 reg_val |= (1 << ICFG_SDIO0_CAP1__SDR104_R); in chal_sd_init()
238 reg_val |= (1 << ICFG_SDIO0_CAP1__SDR50_R); in chal_sd_init()
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/trusted-firmware-a/plat/socionext/synquacer/
A Dsq_bl31_setup.c121 unsigned int reg_val; in sq_configure_sys_timer() local
123 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); in sq_configure_sys_timer()
124 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); in sq_configure_sys_timer()
125 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); in sq_configure_sys_timer()
127 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); in sq_configure_sys_timer()
129 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); in sq_configure_sys_timer()
130 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); in sq_configure_sys_timer()
/trusted-firmware-a/drivers/marvell/mochi/
A Dap807_setup.c319 uint32_t reg_val; in ap807_dram_phy_access_config() local
321 reg_val = mmio_read_32(DSS_SCR_REG); in ap807_dram_phy_access_config()
322 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); in ap807_dram_phy_access_config()
323 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << in ap807_dram_phy_access_config()
325 mmio_write_32(DSS_SCR_REG, reg_val); in ap807_dram_phy_access_config()
A Dcp110_setup.c395 uint32_t reg_val, efuse; in cp110_trng_init() local
398 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); in cp110_trng_init()
399 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; in cp110_trng_init()
400 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); in cp110_trng_init()

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