| /trusted-firmware-a/plat/mediatek/common/drivers/uart/ |
| A D | uart.c | 31 mmio_write_32(UART_EFR(base), uart->registers.efr); in mt_uart_restore()
32 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
33 mmio_write_32(UART_FCR(base), uart->registers.fcr); in mt_uart_restore()
40 uart->registers.lcr | UART_LCR_DLAB); in mt_uart_restore()
41 mmio_write_32(UART_DLL(base), uart->registers.dll); in mt_uart_restore()
42 mmio_write_32(UART_DLH(base), uart->registers.dlh); in mt_uart_restore()
45 uart->registers.sample_count); in mt_uart_restore()
47 uart->registers.sample_point); in mt_uart_restore()
82 uart->registers.lcr | UART_LCR_DLAB); in mt_uart_save()
86 uart->registers.sample_count = mmio_read_32( in mt_uart_save()
[all …]
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| A D | uart.h | 91 struct mt_uart_register registers; member
|
| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 5 | Title | Not saving x0 to x3 registers can leak information from one |
28 into the firmware. However, for an SMC exception, the general purpose registers
32 caller in registers ``x0`` to ``x3``. In TF-A, these return values are written
37 called. It restores the values of all general purpose registers taken from the
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
45 * This function restores all general purpose registers except x30 from the
75 SMCs it would need to be aware of which return registers contain valid data, so
76 it can sanitise any unused return registers. On the other hand, mitigating this
78 information is leaked through registers ``x0`` to ``x3``, by preserving the
82 ``SP_MIN`` already saves all general purpose registers - including ``r0`` to
[all …]
|
| A D | security-advisory-tfv-5.rst | 38 to the list of saved/restored registers both when entering EL3 and also
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-8.rst.txt | 5 | Title | Not saving x0 to x3 registers can leak information from one |
28 into the firmware. However, for an SMC exception, the general purpose registers
32 caller in registers ``x0`` to ``x3``. In TF-A, these return values are written
37 called. It restores the values of all general purpose registers taken from the
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
45 * This function restores all general purpose registers except x30 from the
75 SMCs it would need to be aware of which return registers contain valid data, so
76 it can sanitise any unused return registers. On the other hand, mitigating this
78 information is leaked through registers ``x0`` to ``x3``, by preserving the
82 ``SP_MIN`` already saves all general purpose registers - including ``r0`` to
[all …]
|
| A D | security-advisory-tfv-5.rst.txt | 38 to the list of saved/restored registers both when entering EL3 and also
|
| /trusted-firmware-a/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 40 ``cm_get_context()`` , then programming the registers in the non-secure
43 FIQs to the secure world, the values of the registers can be modified prior
71 X0 (AArch64) and restore other registers as per `SMCCC`_.
77 registers according to `PSCI specification`_ during cold/warm boot.
81 system registers which do not require coordination with the EL3 Runtime
88 registers need to be saved and restored according to `SMCCC`_. In AArch64,
102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
141 data and program the registers as it will done implicitly as part of
148 modify any of the system registers affecting the secure world and instead
[all …]
|
| A D | build-options.rst | 162 the AArch32 system registers to be included when saving and restoring the
174 registers to be included when saving and restoring the CPU context. Default
178 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2
183 registers to be included when saving and restoring the CPU context as
264 MPAM registers without trapping into EL3. This option doesn't make use of
304 registers so are enabled together. Using this option without
328 which are aliased by the SIMD and FP registers. The build option is not
531 wants the timer registers to be saved and restored.
807 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
819 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
[all …]
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | psci-lib-integration-guide.rst.txt | 40 ``cm_get_context()`` , then programming the registers in the non-secure
43 FIQs to the secure world, the values of the registers can be modified prior
71 X0 (AArch64) and restore other registers as per `SMCCC`_.
77 registers according to `PSCI specification`_ during cold/warm boot.
81 system registers which do not require coordination with the EL3 Runtime
88 registers need to be saved and restored according to `SMCCC`_. In AArch64,
102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
141 data and program the registers as it will done implicitly as part of
148 modify any of the system registers affecting the secure world and instead
[all …]
|
| /trusted-firmware-a/tools/marvell/doimage/secure/ |
| A D | sec_img_7K.cfg | 26 # SecureBootControl and EfuseBurnControl registers array
|
| A D | sec_img_8K.cfg | 26 # SecureBootControl and EfuseBurnControl registers array
|
| /trusted-firmware-a/docs/design/ |
| A D | trusted-board-boot-build.rst | 43 root-key storage registers present in the platform. On Juno, these
44 registers are read-only. On FVP Base and Cortex models, the registers
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | trusted-board-boot-build.rst.txt | 43 root-key storage registers present in the platform. On Juno, these
44 registers are read-only. On FVP Base and Cortex models, the registers
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | arm-sip-service.rst.txt | 65 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
72 entered for the first time, following power on. This means CPU registers that
74 registers should not be expected to hold their values before the call was made.
87 Instead, execution starts at the supplied entry point, with the CPU registers 0
|
| /trusted-firmware-a/docs/components/ |
| A D | arm-sip-service.rst | 65 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
72 entered for the first time, following power on. This means CPU registers that
74 registers should not be expected to hold their values before the call was made.
87 Instead, execution starts at the supplied entry point, with the CPU registers 0
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst.txt | 15 - **0x3** = PCIe registers
|
| /trusted-firmware-a/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 15 - **0x3** = PCIe registers
|
| /trusted-firmware-a/docs/perf/ |
| A D | performance-monitoring-unit.rst | 50 ``PMCR`` registers. These can be accessed at all privilege levels.
147 regardless of how the other PMU system registers or bit fields are
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/perf/ |
| A D | performance-monitoring-unit.rst.txt | 50 ``PMCR`` registers. These can be accessed at all privilege levels.
147 regardless of how the other PMU system registers or bit fields are
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/ |
| A D | arm-build-options.rst.txt | 14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
27 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
29 to have a Linux kernel image as BL33 by preparing the registers to these
60 registers.
|
| /trusted-firmware-a/docs/plat/arm/ |
| A D | arm-build-options.rst | 14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
27 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
29 to have a Linux kernel image as BL33 by preparing the registers to these
60 registers.
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/arm_fpga/ |
| A D | index.rst.txt | 30 - ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
34 code (only architectural system registers, and no errata).
|
| /trusted-firmware-a/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 30 - ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
34 code (only architectural system registers, and no errata).
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/threat_model/ |
| A D | threat_model.rst.txt | 63 | | to registers and memory of TF-A. |
77 | | interrupts and registers. |
422 | | values of the registers, privilege level and |
467 | | modify TF-A registers and memory allowing the |
637 | ``Mitigations`` | | TF-A saves and restores registers |
640 | | registers such as floating-point registers. |
737 | | | Non-secure software can configure PMU registers |
|
| /trusted-firmware-a/docs/threat_model/ |
| A D | threat_model.rst | 63 | | to registers and memory of TF-A. |
77 | | interrupts and registers. |
422 | | values of the registers, privilege level and |
467 | | modify TF-A registers and memory allowing the |
637 | ``Mitigations`` | | TF-A saves and restores registers |
640 | | registers such as floating-point registers. |
737 | | | Non-secure software can configure PMU registers |
|