1 /*
2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MT8183_MCUCFG_H
8 #define MT8183_MCUCFG_H
9 
10 #include <platform_def.h>
11 #include <stdint.h>
12 
13 struct mt8183_mcucfg_regs {
14 	uint32_t mp0_ca7l_cache_config;		/* 0x0 */
15 	struct {
16 		uint32_t mem_delsel0;
17 		uint32_t mem_delsel1;
18 	} mp0_cpu[4];				/* 0x4 */
19 	uint32_t mp0_cache_mem_delsel0;		/* 0x24 */
20 	uint32_t mp0_cache_mem_delsel1;		/* 0x28 */
21 	uint32_t mp0_axi_config;		/* 0x2C */
22 	uint32_t mp0_misc_config[10];		/* 0x30 */
23 	uint32_t mp0_ca7l_cfg_dis;		/* 0x58 */
24 	uint32_t mp0_ca7l_clken_ctrl;		/* 0x5C */
25 	uint32_t mp0_ca7l_rst_ctrl;		/* 0x60 */
26 	uint32_t mp0_ca7l_misc_config;		/* 0x64 */
27 	uint32_t mp0_ca7l_dbg_pwr_ctrl;		/* 0x68 */
28 	uint32_t mp0_rw_rsvd0;			/* 0x6C */
29 	uint32_t mp0_rw_rsvd1;			/* 0x70 */
30 	uint32_t mp0_ro_rsvd;			/* 0x74 */
31 	uint32_t reserved0_0;			/* 0x78 */
32 	uint32_t mp0_l2_cache_parity1_rdata;	/* 0x7C */
33 	uint32_t mp0_l2_cache_parity2_rdata;	/* 0x80 */
34 	uint32_t reserved0_1;			/* 0x84 */
35 	uint32_t mp0_rgu_dcm_config;		/* 0x88 */
36 	uint32_t mp0_ca53_specific_ctrl;	/* 0x8C */
37 	uint32_t mp0_esr_case;			/* 0x90 */
38 	uint32_t mp0_esr_mask;			/* 0x94 */
39 	uint32_t mp0_esr_trig_en;		/* 0x98 */
40 	uint32_t reserved_0_2;			/* 0x9C */
41 	uint32_t mp0_ses_cg_en;			/* 0xA0 */
42 	uint32_t reserved0_3[216];		/* 0xA4 */
43 	uint32_t mp_dbg_ctrl;			/* 0x404 */
44 	uint32_t reserved0_4[34];		/* 0x408 */
45 	uint32_t mp_dfd_ctrl;			/* 0x490 */
46 	uint32_t dfd_cnt_l;			/* 0x494 */
47 	uint32_t dfd_cnt_h;			/* 0x498 */
48 	uint32_t misccfg_ro_rsvd;		/* 0x49C */
49 	uint32_t reserved0_5[24];		/* 0x4A0 */
50 	uint32_t mp1_rst_status;		/* 0x500 */
51 	uint32_t mp1_dbg_ctrl;			/* 0x504 */
52 	uint32_t mp1_dbg_flag;			/* 0x508 */
53 	uint32_t mp1_ca7l_ir_mon;		/* 0x50C */
54 	uint32_t reserved0_6[32];		/* 0x510 */
55 	uint32_t mcusys_dbg_mon_sel_a;		/* 0x590 */
56 	uint32_t mcucys_dbg_mon;		/* 0x594 */
57 	uint32_t misccfg_sec_voi_status0;	/* 0x598 */
58 	uint32_t misccfg_sec_vio_status1;	/* 0x59C */
59 	uint32_t reserved0_7[18];		/* 0x5A0 */
60 	uint32_t gic500_int_mask;		/* 0x5E8 */
61 	uint32_t core_rst_en_latch;		/* 0x5EC */
62 	uint32_t reserved0_8[3];		/* 0x5F0 */
63 	uint32_t dbg_core_ret;			/* 0x5FC */
64 	uint32_t mcusys_config_a;		/* 0x600 */
65 	uint32_t mcusys_config1_a;		/* 0x604 */
66 	uint32_t mcusys_gic_prebase_a;		/* 0x608 */
67 	uint32_t mcusys_pinmux;			/* 0x60C */
68 	uint32_t sec_range0_start;		/* 0x610 */
69 	uint32_t sec_range0_end;		/* 0x614 */
70 	uint32_t sec_range_enable;		/* 0x618 */
71 	uint32_t l2c_mm_base;			/* 0x61C */
72 	uint32_t reserved0_9[8];		/* 0x620 */
73 	uint32_t aclken_div;			/* 0x640 */
74 	uint32_t pclken_div;			/* 0x644 */
75 	uint32_t l2c_sram_ctrl;			/* 0x648 */
76 	uint32_t armpll_jit_ctrl;		/* 0x64C */
77 	uint32_t cci_addrmap;			/* 0x650 */
78 	uint32_t cci_config;			/* 0x654 */
79 	uint32_t cci_periphbase;		/* 0x658 */
80 	uint32_t cci_nevntcntovfl;		/* 0x65C */
81 	uint32_t cci_clk_ctrl;			/* 0x660 */
82 	uint32_t cci_acel_s1_ctrl;		/* 0x664 */
83 	uint32_t mcusys_bus_fabric_dcm_ctrl;	/* 0x668 */
84 	uint32_t mcu_misc_dcm_ctrl;		/* 0x66C */
85 	uint32_t xgpt_ctl;			/* 0x670 */
86 	uint32_t xgpt_idx;			/* 0x674 */
87 	uint32_t reserved0_10[3];		/* 0x678 */
88 	uint32_t mcusys_rw_rsvd0;		/* 0x684 */
89 	uint32_t mcusys_rw_rsvd1;		/* 0x688 */
90 	uint32_t reserved0_11[13];		/* 0x68C */
91 	uint32_t gic_500_delsel_ctl;		/* 0x6C0 */
92 	uint32_t etb_delsel_ctl;		/* 0x6C4 */
93 	uint32_t etb_rst_ctl;			/* 0x6C8 */
94 	uint32_t reserved0_12[29];		/* 0x6CC */
95 	uint32_t cci_adb400_dcm_config;		/* 0x740 */
96 	uint32_t sync_dcm_config;		/* 0x744 */
97 	uint32_t reserved0_13;			/* 0x748 */
98 	uint32_t sync_dcm_cluster_config;	/* 0x74C */
99 	uint32_t sw_udi;			/* 0x750 */
100 	uint32_t reserved0_14;			/* 0x754 */
101 	uint32_t gic_sync_dcm;			/* 0x758 */
102 	uint32_t big_dbg_pwr_ctrl;		/* 0x75C */
103 	uint32_t gic_cpu_periphbase;		/* 0x760 */
104 	uint32_t axi_cpu_config;		/* 0x764 */
105 	uint32_t reserved0_15[2];		/* 0x768 */
106 	uint32_t mcsib_sys_ctrl1;		/* 0x770 */
107 	uint32_t mcsib_sys_ctrl2;		/* 0x774 */
108 	uint32_t mcsib_sys_ctrl3;		/* 0x778 */
109 	uint32_t mcsib_sys_ctrl4;		/* 0x77C */
110 	uint32_t mcsib_dbg_ctrl1;		/* 0x780 */
111 	uint32_t pwrmcu_apb2to1;		/* 0x784 */
112 	uint32_t mp0_spmc;			/* 0x788 */
113 	uint32_t reserved0_16;			/* 0x78C */
114 	uint32_t mp0_spmc_sram_ctl;		/* 0x790 */
115 	uint32_t reserved0_17;			/* 0x794 */
116 	uint32_t mp0_sw_rst_wait_cycle;		/* 0x798 */
117 	uint32_t reserved0_18;			/* 0x79C */
118 	uint32_t mp0_pll_divider_cfg;		/* 0x7A0 */
119 	uint32_t reserved0_19;			/* 0x7A4 */
120 	uint32_t mp2_pll_divider_cfg;		/* 0x7A8 */
121 	uint32_t reserved0_20[5];		/* 0x7AC */
122 	uint32_t bus_pll_divider_cfg;		/* 0x7C0 */
123 	uint32_t reserved0_21[7];		/* 0x7C4 */
124 	uint32_t clusterid_aff1;		/* 0x7E0 */
125 	uint32_t clusterid_aff2;		/* 0x7E4 */
126 	uint32_t reserved0_22[2];		/* 0x7E8 */
127 	uint32_t l2_cfg_mp0;			/* 0x7F0 */
128 	uint32_t l2_cfg_mp1;			/* 0x7F4 */
129 	uint32_t reserved0_23[218];		/* 0x7F8 */
130 	uint32_t mscib_dcm_en;			/* 0xB60 */
131 	uint32_t reserved0_24[1063];		/* 0xB64 */
132 	uint32_t cpusys0_sparkvretcntrl;	/* 0x1C00 */
133 	uint32_t cpusys0_sparken;		/* 0x1C04 */
134 	uint32_t cpusys0_amuxsel;		/* 0x1C08 */
135 	uint32_t reserved0_25[9];		/* 0x1C0C */
136 	uint32_t cpusys0_cpu0_spmc_ctl;		/* 0x1C30 */
137 	uint32_t cpusys0_cpu1_spmc_ctl;		/* 0x1C34 */
138 	uint32_t cpusys0_cpu2_spmc_ctl;		/* 0x1C38 */
139 	uint32_t cpusys0_cpu3_spmc_ctl;		/* 0x1C3C */
140 	uint32_t reserved0_26[8];		/* 0x1C40 */
141 	uint32_t mp0_sync_dcm_cgavg_ctrl;	/* 0x1C60 */
142 	uint32_t mp0_sync_dcm_cgavg_fact;	/* 0x1C64 */
143 	uint32_t mp0_sync_dcm_cgavg_rfact;	/* 0x1C68 */
144 	uint32_t mp0_sync_dcm_cgavg;		/* 0x1C6C */
145 	uint32_t mp0_l2_parity_clr;		/* 0x1C70 */
146 	uint32_t reserved0_27[357];		/* 0x1C74 */
147 	uint32_t mp2_cpucfg;			/* 0x2208 */
148 	uint32_t mp2_axi_config;		/* 0x220C */
149 	uint32_t reserved0_28[25];		/* 0x2210 */
150 	uint32_t mp2_sync_dcm;			/* 0x2274 */
151 	uint32_t reserved0_29[10];		/* 0x2278 */
152 	uint32_t ptp3_cputop_spmc0;		/* 0x22A0 */
153 	uint32_t ptp3_cputop_spmc1;		/* 0x22A4 */
154 	uint32_t reserved0_30[98];		/* 0x22A8 */
155 	uint32_t ptp3_cpu0_spmc0;		/* 0x2430 */
156 	uint32_t ptp3_cpu0_spmc1;		/* 0x2434 */
157 	uint32_t ptp3_cpu1_spmc0;		/* 0x2438 */
158 	uint32_t ptp3_cpu1_spmc1;		/* 0x243C */
159 	uint32_t ptp3_cpu2_spmc0;		/* 0x2440 */
160 	uint32_t ptp3_cpu2_spmc1;		/* 0x2444 */
161 	uint32_t ptp3_cpu3_spmc0;		/* 0x2448 */
162 	uint32_t ptp3_cpu3_spmc1;		/* 0x244C */
163 	uint32_t ptp3_cpux_spmc;		/* 0x2450 */
164 	uint32_t reserved0_31[171];		/* 0x2454 */
165 	uint32_t spark2ld0;			/* 0x2700 */
166 };
167 
168 static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
169 
170 enum {
171 	SW_SPARK_EN = 1 << 0,
172 	SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
173 	SW_FSM_OVERRIDE = 1 << 2,
174 	SW_LOGIC_PRE1_PDB = 1 << 3,
175 	SW_LOGIC_PRE2_PDB = 1 << 4,
176 	SW_LOGIC_PDB = 1 << 5,
177 	SW_ISO = 1 << 6,
178 	SW_SRAM_SLEEPB = 0x3f << 7,
179 	SW_SRAM_ISOINTB = 1 << 13,
180 	SW_CLK_DIS = 1 << 14,
181 	SW_CKISO = 1 << 15,
182 	SW_PD = 0x3f << 16,
183 	SW_HOT_PLUG_RESET = 1 << 22,
184 	SW_PWR_ON_OVERRIDE_EN = 1 << 23,
185 	SW_PWR_ON = 1 << 24,
186 	SW_COQ_DIS = 1 << 25,
187 	LOGIC_PDBO_ALL_OFF_ACK = 1 << 26,
188 	LOGIC_PDBO_ALL_ON_ACK = 1 << 27,
189 	LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 28,
190 	LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 29
191 };
192 
193 enum {
194 	CPU_SW_SPARK_EN = 1 << 0,
195 	CPU_SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
196 	CPU_SW_FSM_OVERRIDE = 1 << 2,
197 	CPU_SW_LOGIC_PRE1_PDB = 1 << 3,
198 	CPU_SW_LOGIC_PRE2_PDB = 1 << 4,
199 	CPU_SW_LOGIC_PDB = 1 << 5,
200 	CPU_SW_ISO = 1 << 6,
201 	CPU_SW_SRAM_SLEEPB = 1 << 7,
202 	CPU_SW_SRAM_ISOINTB = 1 << 8,
203 	CPU_SW_CLK_DIS = 1 << 9,
204 	CPU_SW_CKISO = 1 << 10,
205 	CPU_SW_PD = 0x1f << 11,
206 	CPU_SW_HOT_PLUG_RESET = 1 << 16,
207 	CPU_SW_POWR_ON_OVERRIDE_EN = 1 << 17,
208 	CPU_SW_PWR_ON = 1 << 18,
209 	CPU_SPARK2LDO_ALLSWOFF = 1 << 19,
210 	CPU_PDBO_ALL_ON_ACK = 1 << 20,
211 	CPU_PRE2_PDBO_ALLON_ACK = 1 << 21,
212 	CPU_PRE1_PDBO_ALLON_ACK = 1 << 22
213 };
214 
215 enum {
216 	MP2_AXI_CONFIG_ACINACTM = 1 << 0,
217 	MPx_AXI_CONFIG_ACINACTM = 1 << 4,
218 	MPX_CA7_MISC_CONFIG_STANDBYWFIL2 = 1 << 28
219 };
220 
221 enum {
222 	MP0_CPU0_STANDBYWFE = 1 << 20,
223 	MP0_CPU1_STANDBYWFE = 1 << 21,
224 	MP0_CPU2_STANDBYWFE = 1 << 22,
225 	MP0_CPU3_STANDBYWFE = 1 << 23
226 };
227 
228 enum {
229 	MP1_CPU0_STANDBYWFE = 1 << 20,
230 	MP1_CPU1_STANDBYWFE = 1 << 21,
231 	MP1_CPU2_STANDBYWFE = 1 << 22,
232 	MP1_CPU3_STANDBYWFE = 1 << 23
233 };
234 
235 enum {
236 	B_SW_HOT_PLUG_RESET = 1 << 30,
237 	B_SW_PD_OFFSET = 18,
238 	B_SW_PD = 0x3f << B_SW_PD_OFFSET,
239 	B_SW_SRAM_SLEEPB_OFFSET = 12,
240 	B_SW_SRAM_SLEEPB = 0x3f << B_SW_SRAM_SLEEPB_OFFSET
241 };
242 
243 enum {
244 	B_SW_SRAM_ISOINTB = 1 << 9,
245 	B_SW_ISO = 1 << 8,
246 	B_SW_LOGIC_PDB = 1 << 7,
247 	B_SW_LOGIC_PRE2_PDB = 1 << 6,
248 	B_SW_LOGIC_PRE1_PDB = 1 << 5,
249 	B_SW_FSM_OVERRIDE = 1 << 4,
250 	B_SW_PWR_ON = 1 << 3,
251 	B_SW_PWR_ON_OVERRIDE_EN = 1 << 2
252 };
253 
254 enum {
255 	B_FSM_STATE_OUT_OFFSET = 6,
256 	B_FSM_STATE_OUT_MASK = 0x1f << B_FSM_STATE_OUT_OFFSET,
257 	B_SW_LOGIC_PDBO_ALL_OFF_ACK = 1 << 5,
258 	B_SW_LOGIC_PDBO_ALL_ON_ACK = 1 << 4,
259 	B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 3,
260 	B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 2,
261 	B_FSM_OFF = 0 << B_FSM_STATE_OUT_OFFSET,
262 	B_FSM_ON = 1 << B_FSM_STATE_OUT_OFFSET,
263 	B_FSM_RET = 2 << B_FSM_STATE_OUT_OFFSET
264 };
265 
266 /* APB Module infracfg_ao */
267 enum {
268 	INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250,
269 	INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258,
270 	INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8,
271 	INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC
272 };
273 
274 enum {
275 	IDX_PROTECT_MP0_CACTIVE = 10,
276 	IDX_PROTECT_MP1_CACTIVE = 11,
277 	IDX_PROTECT_ICC0_CACTIVE = 12,
278 	IDX_PROTECT_ICD0_CACTIVE = 13,
279 	IDX_PROTECT_ICC1_CACTIVE = 14,
280 	IDX_PROTECT_ICD1_CACTIVE = 15,
281 	IDX_PROTECT_L2C0_CACTIVE = 26,
282 	IDX_PROTECT_L2C1_CACTIVE = 27
283 };
284 
285 /* cpu boot mode */
286 enum {
287 	MP0_CPUCFG_64BIT_SHIFT = 12,
288 	MP1_CPUCFG_64BIT_SHIFT = 28,
289 	MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
290 	MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT
291 };
292 
293 /* scu related */
294 enum {
295 	MP0_ACINACTM_SHIFT = 4,
296 	MP1_ACINACTM_SHIFT = 4,
297 	MP2_ACINACTM_SHIFT = 0,
298 	MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
299 	MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT,
300 	MP2_ACINACTM = 1 << MP2_ACINACTM_SHIFT
301 };
302 
303 enum {
304 	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
305 	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
306 	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
307 	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
308 	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
309 
310 	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
311 		0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
312 	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
313 		0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
314 	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
315 		0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
316 	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
317 		0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
318 	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
319 		0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
320 };
321 
322 enum {
323 	MP1_AINACTS_SHIFT = 4,
324 	MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
325 };
326 
327 enum {
328 	MP1_SW_CG_GEN_SHIFT = 12,
329 	MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
330 };
331 
332 enum {
333 	MP1_L2RSTDISABLE_SHIFT = 14,
334 	MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
335 };
336 
337 /* bus pll divider dcm related */
338 enum {
339 	BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT = 11,
340 	BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
341 	BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
342 
343 	BUS_PLLDIV_DCM = (1 << BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT) |
344 			 (1 << BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
345 			 (1 << BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT)
346 };
347 
348 /* mp0 pll divider dcm related */
349 enum {
350 	MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11,
351 	MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
352 	MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
353 	MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31,
354 	MP0_PLLDIV_DCM = (1 << MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT) |
355 			 (1 << MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
356 			 (1 << MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT) |
357 			 (1u << MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT)
358 };
359 
360 /* mp2 pll divider dcm related */
361 enum {
362 	MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11,
363 	MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
364 	MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
365 	MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31,
366 	MP2_PLLDIV_DCM = (1 << MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT) |
367 			 (1 << MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
368 			 (1 << MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT) |
369 			 (1u << MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT)
370 };
371 
372 /* mcsib dcm related */
373 enum {
374 	MCSIB_CACTIVE_SEL_SHIFT = 0,
375 	MCSIB_DCM_EN_SHIFT = 16,
376 
377 	MCSIB_CACTIVE_SEL_MASK = 0xffff << MCSIB_CACTIVE_SEL_SHIFT,
378 	MCSIB_CACTIVE_SEL = 0xffff << MCSIB_CACTIVE_SEL_SHIFT,
379 
380 	MCSIB_DCM_MASK = 0xffffu << MCSIB_DCM_EN_SHIFT,
381 	MCSIB_DCM = 0xffffu << MCSIB_DCM_EN_SHIFT,
382 };
383 
384 /* cci adb400 dcm related */
385 enum {
386 	CCI_M0_ADB400_DCM_EN_SHIFT = 0,
387 	CCI_M1_ADB400_DCM_EN_SHIFT = 1,
388 	CCI_M2_ADB400_DCM_EN_SHIFT = 2,
389 	CCI_S2_ADB400_DCM_EN_SHIFT = 3,
390 	CCI_S3_ADB400_DCM_EN_SHIFT = 4,
391 	CCI_S4_ADB400_DCM_EN_SHIFT = 5,
392 	CCI_S5_ADB400_DCM_EN_SHIFT = 6,
393 	ACP_S3_ADB400_DCM_EN_SHIFT = 11,
394 
395 	CCI_ADB400_DCM_MASK = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) |
396 			      (1 << CCI_M1_ADB400_DCM_EN_SHIFT) |
397 			      (1 << CCI_M2_ADB400_DCM_EN_SHIFT) |
398 			      (1 << CCI_S2_ADB400_DCM_EN_SHIFT) |
399 			      (1 << CCI_S4_ADB400_DCM_EN_SHIFT) |
400 			      (1 << CCI_S4_ADB400_DCM_EN_SHIFT) |
401 			      (1 << CCI_S5_ADB400_DCM_EN_SHIFT) |
402 			      (1 << ACP_S3_ADB400_DCM_EN_SHIFT),
403 	CCI_ADB400_DCM = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) |
404 			 (1 << CCI_M1_ADB400_DCM_EN_SHIFT) |
405 			 (1 << CCI_M2_ADB400_DCM_EN_SHIFT) |
406 			 (0 << CCI_S2_ADB400_DCM_EN_SHIFT) |
407 			 (0 << CCI_S4_ADB400_DCM_EN_SHIFT) |
408 			 (0 << CCI_S4_ADB400_DCM_EN_SHIFT) |
409 			 (0 << CCI_S5_ADB400_DCM_EN_SHIFT) |
410 			 (1 << ACP_S3_ADB400_DCM_EN_SHIFT)
411 };
412 
413 /* sync dcm related */
414 enum {
415 	CCI_SYNC_DCM_DIV_EN_SHIFT = 0,
416 	CCI_SYNC_DCM_UPDATE_TOG_SHIFT = 1,
417 	CCI_SYNC_DCM_DIV_SEL_SHIFT = 2,
418 	MP0_SYNC_DCM_DIV_EN_SHIFT = 10,
419 	MP0_SYNC_DCM_UPDATE_TOG_SHIFT = 11,
420 	MP0_SYNC_DCM_DIV_SEL_SHIFT = 12,
421 
422 	SYNC_DCM_MASK = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) |
423 			(1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) |
424 			(0x7f << CCI_SYNC_DCM_DIV_SEL_SHIFT) |
425 			(1 << MP0_SYNC_DCM_DIV_EN_SHIFT) |
426 			(1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) |
427 			(0x7f << MP0_SYNC_DCM_DIV_SEL_SHIFT),
428 	SYNC_DCM = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) |
429 		   (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) |
430 		   (0 << CCI_SYNC_DCM_DIV_SEL_SHIFT) |
431 		   (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) |
432 		   (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) |
433 		   (0 << MP0_SYNC_DCM_DIV_SEL_SHIFT)
434 };
435 
436 /* mcu bus dcm related */
437 enum {
438 	MCU_BUS_DCM_EN_SHIFT = 8,
439 	MCU_BUS_DCM = 1 << MCU_BUS_DCM_EN_SHIFT
440 };
441 
442 /* mcusys bus fabric dcm related */
443 enum {
444 	ACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 0,
445 	EMI2_ADB400_S_DCM_CTRL_SHIFT = 1,
446 	ACLK_GPU_DYNAMIC_CG_EN_SHIFT = 2,
447 	ACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 3,
448 	MP0_ADB400_S_DCM_CTRL_SHIFT = 4,
449 	MP0_ADB400_M_DCM_CTRL_SHIFT = 5,
450 	MP1_ADB400_S_DCM_CTRL_SHIFT = 6,
451 	MP1_ADB400_M_DCM_CTRL_SHIFT = 7,
452 	EMICLK_EMI_DYNAMIC_CG_EN_SHIFT = 8,
453 	INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 9,
454 	EMICLK_GPU_DYNAMIC_CG_EN_SHIFT = 10,
455 	INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 11,
456 	EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT = 12,
457 	EMI1_ADB400_S_DCM_CTRL_SHIFT = 16,
458 	MP2_ADB400_M_DCM_CTRL_SHIFT = 17,
459 	MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT = 18,
460 	MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT = 19,
461 	MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT = 20,
462 	L2_SHARE_ADB400_DCM_CTRL_SHIFT = 21,
463 	MP1_AGGRESS_DCM_CTRL_SHIFT = 22,
464 	MP0_AGGRESS_DCM_CTRL_SHIFT = 23,
465 	MP0_ADB400_ACP_S_DCM_CTRL_SHIFT = 24,
466 	MP0_ADB400_ACP_M_DCM_CTRL_SHIFT = 25,
467 	MP1_ADB400_ACP_S_DCM_CTRL_SHIFT = 26,
468 	MP1_ADB400_ACP_M_DCM_CTRL_SHIFT = 27,
469 	MP3_ADB400_M_DCM_CTRL_SHIFT = 28,
470 	MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT = 29,
471 
472 	MCUSYS_BUS_FABRIC_DCM_MASK = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
473 				     (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) |
474 				     (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) |
475 				     (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
476 				     (1 << MP0_ADB400_S_DCM_CTRL_SHIFT) |
477 				     (1 << MP0_ADB400_M_DCM_CTRL_SHIFT) |
478 				     (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) |
479 				     (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) |
480 				     (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) |
481 				     (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
482 				     (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) |
483 				     (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
484 				     (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) |
485 				     (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) |
486 				     (1 << MP2_ADB400_M_DCM_CTRL_SHIFT) |
487 				     (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
488 				     (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
489 				     (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
490 				     (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) |
491 				     (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) |
492 				     (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) |
493 				     (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) |
494 				     (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) |
495 				     (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) |
496 				     (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) |
497 				     (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) |
498 				     (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT),
499 
500 	MCUSYS_BUS_FABRIC_DCM = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
501 				(1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) |
502 				(1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) |
503 				(1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
504 				(0 << MP0_ADB400_S_DCM_CTRL_SHIFT) |
505 				(0 << MP0_ADB400_M_DCM_CTRL_SHIFT) |
506 				(1 << MP1_ADB400_S_DCM_CTRL_SHIFT) |
507 				(1 << MP1_ADB400_M_DCM_CTRL_SHIFT) |
508 				(1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) |
509 				(1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
510 				(1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) |
511 				(1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
512 				(1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) |
513 				(1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) |
514 				(0 << MP2_ADB400_M_DCM_CTRL_SHIFT) |
515 				(1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
516 				(1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
517 				(1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
518 				(1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) |
519 				(1 << MP1_AGGRESS_DCM_CTRL_SHIFT) |
520 				(1 << MP0_AGGRESS_DCM_CTRL_SHIFT) |
521 				(1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) |
522 				(1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) |
523 				(1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) |
524 				(1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) |
525 				(1 << MP3_ADB400_M_DCM_CTRL_SHIFT) |
526 				(1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT)
527 };
528 
529 /* l2c_sram dcm related */
530 enum {
531 	L2C_SRAM_DCM_EN_SHIFT = 0,
532 	L2C_SRAM_DCM = 1 << L2C_SRAM_DCM_EN_SHIFT
533 };
534 
535 /* mcu misc dcm related */
536 enum {
537 	MP0_CNTVALUEB_DCM_EN_SHIFT = 0,
538 	MP_CNTVALUEB_DCM_EN = 8,
539 
540 	CNTVALUEB_DCM = (1 << MP0_CNTVALUEB_DCM_EN_SHIFT) |
541 			(1 << MP_CNTVALUEB_DCM_EN)
542 };
543 
544 /* sync dcm cluster config related */
545 enum {
546 	MP0_SYNC_DCM_STALL_WR_EN_SHIFT = 7,
547 	MCUSYS_MAX_ACCESS_LATENCY_SHIFT = 24,
548 
549 	MCU0_SYNC_DCM_STALL_WR_EN = 1 << MP0_SYNC_DCM_STALL_WR_EN_SHIFT,
550 
551 	MCUSYS_MAX_ACCESS_LATENCY_MASK = 0xf << MCUSYS_MAX_ACCESS_LATENCY_SHIFT,
552 	MCUSYS_MAX_ACCESS_LATENCY = 0x5 << MCUSYS_MAX_ACCESS_LATENCY_SHIFT
553 };
554 
555 /* cpusys rgu dcm related */
556 enum {
557 	CPUSYS_RGU_DCM_CONFIG_SHIFT = 0,
558 
559 	CPUSYS_RGU_DCM_CINFIG = 1 << CPUSYS_RGU_DCM_CONFIG_SHIFT
560 };
561 
562 /* mp2 sync dcm related */
563 enum {
564 	MP2_DCM_EN_SHIFT = 0,
565 
566 	MP2_DCM_EN = 1 << MP2_DCM_EN_SHIFT
567 };
568 #endif  /* MT8183_MCUCFG_H */
569