Searched refs:row (Results 1 – 9 of 9) sorted by relevance
| /trusted-firmware-a/drivers/brcm/ |
| A D | sotp.c | 262 int row; in sotp_read_key() local
269 row = start_row; in sotp_read_key()
270 while ((keysize > 0) && (row <= end_row)) { in sotp_read_key()
271 row_data = sotp_mem_read(row, SOTP_ROW_ECC); in sotp_read_key()
279 row++; in sotp_read_key()
282 if ((status2 == 0xFFFFFFFF) || (status == 0) || (row > end_row)) in sotp_read_key()
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| /trusted-firmware-a/drivers/renesas/common/ddr/ddr_b/ |
| A D | boot_init_dram_regdef.h | 24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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| /trusted-firmware-a/lib/zlib/ |
| A D | crc32.c | 378 unsigned long row; local
388 row = 1;
390 odd[n] = row;
391 row <<= 1;
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| /trusted-firmware-a/plat/intel/soc/agilex/soc/ |
| A D | agilex_memory_controller.c | 175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
190 row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /trusted-firmware-a/plat/intel/soc/stratix10/soc/ |
| A D | s10_memory_controller.c | 204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
219 row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /trusted-firmware-a/docs/build/latex/ |
| A D | sphinxlatextables.sty | 306 % It turns out \CT@row@color is not expanded contrarily to \CT@column@color
309 % row color and cell color. It would even be possible to propagate cell color
310 % to row color for the duration of the Sphinx multicolumn... the (provisional?)
333 \ifnum#1>\@ne % multi-column (and possibly also multi-row)
435 % arrange for each row to have enough space for:
457 % LaTeX typesets the table row by row, hence each execution can do
458 % an update for the next row.
468 % next row will be with a #2 decremented by one
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| A D | sphinxlatexobjects.sty | 98 % used twice or more in a row for labels sharing common description,
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| A D | trustedfirmware-a.log | 89 \row@=\count186
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| /trusted-firmware-a/plat/rockchip/rk3399/drivers/dram/ |
| A D | dfs.c | 89 uint32_t row; in get_cs_die_capability() local
91 row = cs == 0 ? ch->cs0_row : ch->cs1_row; in get_cs_die_capability()
95 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + in get_cs_die_capability()
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