| /trusted-firmware-a/fdts/ |
| A D | stm32mp151.dtsi | 207 st,tzcr = <&rcc 0x0 0x1>;
255 st,irq-number = <6>;
523 st,bank-name = "GPIOA";
534 st,bank-name = "GPIOB";
545 st,bank-name = "GPIOC";
556 st,bank-name = "GPIOD";
567 st,bank-name = "GPIOE";
578 st,bank-name = "GPIOF";
589 st,bank-name = "GPIOG";
600 st,bank-name = "GPIOH";
[all …]
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| A D | stm32mp15-ddr.dtsi | 7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <DDR_MEM_SIZE>;
11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
86 st,phy-reg = <
100 st,phy-timing = <
113 st,phy-cal = <
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| A D | stm32mp157c-ed1.dts | 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
42 st,digbypass;
110 st,mask-reset;
205 st,clksrc = <
217 st,clkdiv = <
231 st,pkcs = <
270 pll1: st,pll@0 {
313 st,sig-dir;
314 st,neg-edge;
315 st,use-ckin;
[all …]
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| A D | stm32mp157a-avenger96.dts | 90 st,mask-reset;
178 st,clksrc = <
190 st,clkdiv = <
204 st,pkcs = <
243 pll1: st,pll@0 {
251 pll2: st,pll@1 {
259 pll3: st,pll@2 {
267 pll4: st,pll@3 {
285 st,sig-dir;
286 st,neg-edge;
[all …]
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| A D | stm32mp15xx-osd32.dtsi | 18 compatible = "st,stpmic1";
54 st,mask-reset;
164 st,non-secure-otp;
169 st,digbypass;
187 st,clksrc = <
199 st,clkdiv = <
213 st,pkcs = <
252 pll1: st,pll@0 {
260 pll2: st,pll@1 {
268 pll3: st,pll@2 {
[all …]
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| A D | stm32mp157c-odyssey-som.dtsi | 33 st,non-secure-otp;
38 st,digbypass;
113 st,mask-reset;
209 st,clksrc = <
221 st,clkdiv = <
235 st,pkcs = <
274 pll1: st,pll@0 {
282 pll2: st,pll@1 {
290 pll3: st,pll@2 {
298 pll4: st,pll@3 {
[all …]
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| A D | stm32mp15xx-dkx.dtsi | 28 st,non-secure-otp;
33 st,digbypass;
104 st,mask-reset;
195 st,clksrc = <
207 st,clkdiv = <
221 st,pkcs = <
260 pll1: st,pll@0 {
268 pll2: st,pll@1 {
276 pll3: st,pll@2 {
284 pll4: st,pll@3 {
[all …]
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| A D | stm32mp157c-ev1.dts | 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
12 compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
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| A D | stm32mp157a-dk1.dts | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
16 compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
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| A D | stm32mp157c-dk2.dts | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
17 compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
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| A D | stm32mp15xxac-pinctrl.dtsi | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
8 st,package = <STM32MP_PKG_AC>;
66 st,package = <STM32MP_PKG_AC>;
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| A D | stm32mp15xxaa-pinctrl.dtsi | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
8 st,package = <STM32MP_PKG_AA>;
78 st,package = <STM32MP_PKG_AA>;
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| A D | stm32mp15xc.dtsi | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
10 compatible = "st,stm32mp1-cryp";
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| /trusted-firmware-a/plat/st/stm32mp1/sp_min/ |
| A D | sp_min-stm32mp1.mk | 11 BL32_SOURCES += drivers/st/etzpc/etzpc.c \
13 plat/st/stm32mp1/sp_min/sp_min_setup.c \
14 plat/st/stm32mp1/stm32mp1_pm.c \
15 plat/st/stm32mp1/stm32mp1_shared_resources.c \
16 plat/st/stm32mp1/stm32mp1_topology.c
27 plat/st/stm32mp1/stm32mp1_gic.c
40 BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
41 plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
42 plat/st/stm32mp1/stm32mp1_scmi.c
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| /trusted-firmware-a/drivers/rpi3/mailbox/ |
| A D | rpi3_mbox.c | 24 uint32_t st, data; in rpi3_vc_mailbox_request_send() local
38 st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); in rpi3_vc_mailbox_request_send()
46 } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); in rpi3_vc_mailbox_request_send()
56 st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); in rpi3_vc_mailbox_request_send()
64 } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); in rpi3_vc_mailbox_request_send()
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| /trusted-firmware-a/plat/mediatek/common/ |
| A D | mtk_cirq.c | 301 uint32_t addr, st, val; in mt_irq_get_en() local
304 st = mmio_read_32(addr); in mt_irq_get_en()
306 val = (st >> (irq % 32U)) & 1U; in mt_irq_get_en()
450 uint32_t st; in mt_cirq_enable() local
455 st = mmio_read_32(CIRQ_CON); in mt_cirq_enable()
459 st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS); in mt_cirq_enable()
469 uint32_t st; in mt_cirq_disable() local
471 st = mmio_read_32(CIRQ_CON); in mt_cirq_disable()
544 uint32_t st; in mt_cirq_sw_reset() local
546 st = mmio_read_32(CIRQ_CON); in mt_cirq_sw_reset()
[all …]
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| /trusted-firmware-a/plat/rockchip/px30/drivers/secure/ |
| A D | secure.c | 22 uintptr_t st, size_t sz) in secure_ddr_region() argument
24 uintptr_t ed = st + sz; in secure_ddr_region()
29 assert(st < ed); in secure_ddr_region()
32 assert(st % SIZE_M(1) == 0); in secure_ddr_region()
35 st_mb = st / SIZE_M(1); in secure_ddr_region()
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| /trusted-firmware-a/plat/rockchip/rk3288/drivers/secure/ |
| A D | secure.c | 50 static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz) in sgrf_ddr_rgn_config() argument
52 uintptr_t ed = st + sz; in sgrf_ddr_rgn_config()
56 assert(st < ed); in sgrf_ddr_rgn_config()
59 assert(st % SIZE_M(1) == 0); in sgrf_ddr_rgn_config()
62 st_mb = st / SIZE_M(1); in sgrf_ddr_rgn_config()
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| /trusted-firmware-a/plat/rockchip/rk3399/drivers/secure/ |
| A D | secure.c | 58 uintptr_t st, size_t sz) in sgrf_ddr_rgn_config() argument
60 uintptr_t ed = st + sz; in sgrf_ddr_rgn_config()
64 assert(st < ed); in sgrf_ddr_rgn_config()
67 assert(st % SIZE_M(1) == 0); in sgrf_ddr_rgn_config()
70 st_mb = st / SIZE_M(1); in sgrf_ddr_rgn_config()
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| /trusted-firmware-a/include/lib/libc/ |
| A D | stddef.h | 25 #define offsetof(st, m) __builtin_offsetof(st, m) argument
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| /trusted-firmware-a/docs/about/ |
| A D | release-information.rst | 37 | v2.0 | 1st week of Oct '18 | 1st week of Sep '18 |
39 | v2.1 | 5th week of Mar '19 | 1st week of Mar '19 |
41 | v2.2 | 4th week of Oct '19 | 1st week of Oct '19 |
43 | v2.3 | 4th week of Apr '20 | 1st week of Apr '20 |
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/about/ |
| A D | release-information.rst.txt | 37 | v2.0 | 1st week of Oct '18 | 1st week of Sep '18 |
39 | v2.1 | 5th week of Mar '19 | 1st week of Mar '19 |
41 | v2.2 | 4th week of Oct '19 | 1st week of Oct '19 |
43 | v2.3 | 4th week of Apr '20 | 1st week of Apr '20 |
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| /trusted-firmware-a/services/spd/opteed/ |
| A D | opteed_private.h | 30 #define set_optee_pstate(st, pst) do { \ argument
31 clr_optee_pstate(st); \
32 st |= (pst & OPTEE_PSTATE_MASK) << \
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| /trusted-firmware-a/plat/common/ |
| A D | plat_psci_common.c | 153 const plat_local_state_t *st = states; in plat_get_target_pwr_state() local
159 temp = *st; in plat_get_target_pwr_state()
160 st++; in plat_get_target_pwr_state()
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| /trusted-firmware-a/plat/mediatek/mt8195/drivers/spm/ |
| A D | mt_spm_constraint.h | 45 #define IS_MT_SPM_RC_BBLPM_MODE(st) \ argument
46 ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
|