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Searched refs:state (Results 1 – 25 of 210) sorted by relevance

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/trusted-firmware-a/lib/zlib/
A Dinflate.c137 state->lencode = state->distcode = state->next = state->codes;
423 zmemcpy(state->window, end - state->wsize, state->wsize);
425 state->whave = state->wsize;
435 state->whave = state->wsize;
439 if (state->wnext == state->wsize) state->wnext = 0;
440 if (state->whave < state->wsize) state->whave += dist;
946 state->next = state->codes;
960 while (state->have < state->nlen + state->ndist) {
1020 state->next = state->codes;
1101 state->was = state->length;
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A Dinffast.c81 state = (struct inflate_state FAR *)strm->state;
88 dmax = state->dmax;
90 wsize = state->wsize;
91 whave = state->whave;
92 wnext = state->wnext;
93 window = state->window;
94 hold = state->hold;
95 bits = state->bits;
96 lcode = state->lencode;
304 state->hold = hold;
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/trusted-firmware-a/plat/mediatek/mt8195/
A Dplat_pm.c96 if (IS_MCUSYS_OFF_STATE(state)) { in plat_cpu_pwron_common()
224 if (IS_CLUSTER_OFF_STATE(state)) { in plat_power_domain_on_finish()
225 plat_cluster_pwron_common(cpu, state, 0U); in plat_power_domain_on_finish()
228 plat_cpu_pwron_common(cpu, state, 0U); in plat_power_domain_on_finish()
238 plat_cpu_pwrdwn_common(cpu, state, 0U); in plat_power_domain_off()
244 if (IS_CLUSTER_OFF_STATE(state)) { in plat_power_domain_off()
245 plat_cluster_pwrdwn_common(cpu, state, 0U); in plat_power_domain_off()
260 if (IS_CLUSTER_OFF_STATE(state)) { in plat_power_domain_suspend()
265 if (IS_MCUSYS_OFF_STATE(state)) { in plat_power_domain_suspend()
277 if (IS_MCUSYS_OFF_STATE(state)) { in plat_power_domain_suspend_finish()
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/trusted-firmware-a/plat/mediatek/mt8192/
A Dplat_pm.c95 if (IS_MCUSYS_OFF_STATE(state)) { in plat_cpu_pwron_common()
226 if (IS_CLUSTER_OFF_STATE(state)) { in plat_power_domain_on_finish()
227 plat_cluster_pwron_common(cpu, state, 0U); in plat_power_domain_on_finish()
230 plat_cpu_pwron_common(cpu, state, 0U); in plat_power_domain_on_finish()
240 plat_cpu_pwrdwn_common(cpu, state, 0U); in plat_power_domain_off()
246 if (IS_CLUSTER_OFF_STATE(state)) { in plat_power_domain_off()
247 plat_cluster_pwrdwn_common(cpu, state, 0U); in plat_power_domain_off()
262 if (IS_CLUSTER_OFF_STATE(state)) { in plat_power_domain_suspend()
267 if (IS_MCUSYS_OFF_STATE(state)) { in plat_power_domain_suspend()
279 if (IS_MCUSYS_OFF_STATE(state)) { in plat_power_domain_suspend_finish()
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/trusted-firmware-a/plat/mediatek/mt8192/drivers/mcdi/
A Dmt_cpu_pm.c25 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
30 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
34 if (IS_SYSTEM_SUSPEND_STATE(state)) { in pwr_state_reflect()
41 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
46 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
66 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron()
76 const psci_power_state_t *state) in pwr_mcusys_pwron_finished() argument
78 int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS]; in pwr_mcusys_pwron_finished()
80 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron_finished()
92 int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS]; in pwr_mcusys_pwrdwn()
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/trusted-firmware-a/plat/mediatek/mt8195/drivers/mcdi/
A Dmt_cpu_pm.c25 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
30 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
34 if (IS_SYSTEM_SUSPEND_STATE(state)) { in pwr_state_reflect()
41 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
46 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
66 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron()
76 const psci_power_state_t *state) in pwr_mcusys_pwron_finished() argument
78 int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS]; in pwr_mcusys_pwron_finished()
80 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron_finished()
92 int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS]; in pwr_mcusys_pwrdwn()
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/trusted-firmware-a/drivers/renesas/common/iic_dvfs/
A Diic_dvfs.c153 *state = DVFS_START; in IIC_DVFS_FUNC()
183 *state = DVFS_START; in IIC_DVFS_FUNC()
234 *state = DVFS_SET_SLAVE; in IIC_DVFS_FUNC()
261 *state = DVFS_WRITE_ADDR; in IIC_DVFS_FUNC()
312 *state = DVFS_STOP; in IIC_DVFS_FUNC()
337 *state = DVFS_DONE; in IIC_DVFS_FUNC()
462 *state = DVFS_STOP_READ; in IIC_DVFS_FUNC()
490 *state = DVFS_READ; in IIC_DVFS_FUNC()
508 *state = DVFS_DONE; in IIC_DVFS_FUNC()
522 switch (state) { in RCAR_DVFS_API()
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/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dnvg.c27 if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && in nvg_enter_cstate()
28 (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { in nvg_enter_cstate()
29 ERROR("%s: unknown cstate (%d)\n", __func__, state); in nvg_enter_cstate()
37 write_actlr_el1(val | (uint64_t)state); in nvg_enter_cstate()
120 if (state == 0U) { in nvg_read_cstate_stats()
130 (uint64_t)state)); in nvg_read_cstate_stats()
158 (uint64_t)state), val); in nvg_write_cstate_stats()
166 (void)state; in nvg_is_ccx_allowed()
181 if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && in nvg_is_sc7_allowed()
182 (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { in nvg_is_sc7_allowed()
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/trusted-firmware-a/lib/extensions/sme/
A Dsme.c36 el3_state_t *state; in sme_enable() local
44 state = get_el3state_ctx(context); in sme_enable()
47 reg = read_ctx_reg(state, CTX_CPTR_EL3); in sme_enable()
49 write_ctx_reg(state, CTX_CPTR_EL3, reg); in sme_enable()
52 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_enable()
54 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_enable()
82 el3_state_t *state; in sme_disable() local
90 state = get_el3state_ctx(context); in sme_disable()
93 reg = read_ctx_reg(state, CTX_CPTR_EL3); in sme_disable()
100 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_disable()
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/trusted-firmware-a/plat/mediatek/mt8192/include/
A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
35 const psci_power_state_t *state);
37 const psci_power_state_t *state);
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
41 const psci_power_state_t *state);
43 const psci_power_state_t *state);
/trusted-firmware-a/plat/mediatek/mt8195/include/
A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
35 const psci_power_state_t *state);
37 const psci_power_state_t *state);
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
41 const psci_power_state_t *state);
43 const psci_power_state_t *state);
/trusted-firmware-a/drivers/renesas/common/emmc/
A Demmc_cmd.c203 EMMC_INT_STATE state; in emmc_exec_cmd() local
223 state = ESTATE_BEGIN; in emmc_exec_cmd()
240 switch (state) { in emmc_exec_cmd()
286 state = ESTATE_ERROR; in emmc_exec_cmd()
291 state = ESTATE_ERROR; in emmc_exec_cmd()
294 state = ESTATE_END; in emmc_exec_cmd()
316 state = ESTATE_ERROR; in emmc_exec_cmd()
322 state = ESTATE_ERROR; in emmc_exec_cmd()
367 state = ESTATE_END; in emmc_exec_cmd()
443 state = ESTATE_END; in emmc_exec_cmd()
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/trusted-firmware-a/plat/nxp/common/psci/
A Dplat_psci.c183 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend()
258 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend_finish()
339 psci_power_state_t *state) in _pwr_state_validate() argument
348 state->pwr_domain_state[PLAT_MAX_LVL] = in _pwr_state_validate()
351 state->pwr_domain_state[PLAT_MAX_LVL] = in _pwr_state_validate()
356 state->pwr_domain_state[PLAT_SYS_LVL] = in _pwr_state_validate()
359 state->pwr_domain_state[PLAT_SYS_LVL] = in _pwr_state_validate()
364 state->pwr_domain_state[PLAT_CLSTR_LVL] = in _pwr_state_validate()
367 state->pwr_domain_state[PLAT_CLSTR_LVL] = in _pwr_state_validate()
374 state->pwr_domain_state[PLAT_CORE_LVL] = in _pwr_state_validate()
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/trusted-firmware-a/plat/mediatek/mt8173/
A Dplat_pm.c37 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] argument
38 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] argument
40 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
302 if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { in plat_power_domain_off()
339 if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) { in plat_power_domain_suspend()
341 if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) in plat_power_domain_suspend()
348 if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { in plat_power_domain_suspend()
353 if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { in plat_power_domain_suspend()
409 if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { in plat_power_domain_suspend_finish()
425 if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) { in plat_power_domain_suspend_finish()
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/trusted-firmware-a/services/std_svc/sdei/
A Dsdei_intr_mgmt.c69 if (!state->pe_masked) { in sdei_pe_mask()
70 state->pe_masked = true; in sdei_pe_mask()
112 state->pe_masked = false; in sdei_pe_unmask()
124 disp_ctx = &state->dispatch_stack[state->stack_top]; in push_dispatch()
125 state->stack_top++; in push_dispatch()
140 state->stack_top--; in pop_dispatch()
142 return &state->dispatch_stack[state->stack_top]; in pop_dispatch()
155 return &state->dispatch_stack[state->stack_top - 1U]; in get_outstanding_dispatch()
415 sdei_cpu_state_t *state; in sdei_intr_handler() local
459 if (state->pe_masked) { in sdei_intr_handler()
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/trusted-firmware-a/services/spd/tspd/
A Dtspd_private.h26 #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) argument
27 #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ argument
47 #define get_yield_smc_active_flag(state) \ argument
48 ((state >> YIELD_SMC_ACTIVE_FLAG_SHIFT) \
50 #define set_yield_smc_active_flag(state) (state |= \ argument
52 #define clr_yield_smc_active_flag(state) (state &= \ argument
184 uint32_t state; member
A Dtspd_pm.c37 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); in tspd_cpu_off_handler()
60 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); in tspd_cpu_off_handler()
76 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); in tspd_cpu_suspend_handler()
96 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); in tspd_cpu_suspend_handler()
113 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); in tspd_cpu_on_finish_handler()
142 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); in tspd_cpu_on_finish_handler()
157 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); in tspd_cpu_suspend_finish_handler()
174 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); in tspd_cpu_suspend_finish_handler()
196 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); in tspd_system_off()
222 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); in tspd_system_reset()
/trusted-firmware-a/plat/imx/imx8m/include/
A Dimx8m_psci.h10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
12 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) argument
/trusted-firmware-a/plat/brcm/common/
A Dbrcm_scpi.c129 uint32_t state = 0; in scpi_set_brcm_power_state() local
137 state |= (mpidr >> MPIDR_AFF1_SHIFT) & 0x0f; /* CPU ID */ in scpi_set_brcm_power_state()
138 state |= ((mpidr >> MPIDR_AFF2_SHIFT) & 0x0f) << 4; /* Cluster ID */ in scpi_set_brcm_power_state()
140 state |= mpidr & 0x0f; /* CPU ID */ in scpi_set_brcm_power_state()
141 state |= (mpidr & 0xf00) >> 4; /* Cluster ID */ in scpi_set_brcm_power_state()
144 state |= cpu_state << 8; in scpi_set_brcm_power_state()
145 state |= cluster_state << 12; in scpi_set_brcm_power_state()
146 state |= brcm_state << 16; in scpi_set_brcm_power_state()
155 cmd->size = sizeof(state); in scpi_set_brcm_power_state()
158 *payload_addr = state; in scpi_set_brcm_power_state()
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/trusted-firmware-a/services/spd/tlkd/
A Dtlkd_private.h28 #define get_yield_smc_active_flag(state) \ argument
29 (((state) >> YIELD_SMC_ACTIVE_FLAG_SHIFT) \
31 #define set_yield_smc_active_flag(state) ((state) |= \ argument
33 #define clr_yield_smc_active_flag(state) ((state) &= \ argument
102 uint32_t state; member
/trusted-firmware-a/drivers/arm/css/scpi/
A Dcss_scpi.c134 uint32_t state = 0; in scpi_set_css_power_state() local
142 state |= (mpidr >> MPIDR_AFF1_SHIFT) & 0x0f; /* CPU ID */ in scpi_set_css_power_state()
143 state |= ((mpidr >> MPIDR_AFF2_SHIFT) & 0x0f) << 4; /* Cluster ID */ in scpi_set_css_power_state()
145 state |= mpidr & 0x0f; /* CPU ID */ in scpi_set_css_power_state()
146 state |= (mpidr & 0xf00) >> 4; /* Cluster ID */ in scpi_set_css_power_state()
149 state |= cpu_state << 8; in scpi_set_css_power_state()
150 state |= cluster_state << 12; in scpi_set_css_power_state()
151 state |= css_state << 16; in scpi_set_css_power_state()
160 cmd->size = sizeof(state); in scpi_set_css_power_state()
163 *payload_addr = state; in scpi_set_css_power_state()
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/trusted-firmware-a/services/spd/opteed/
A Dopteed_pm.c36 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); in opteed_cpu_off_handler()
53 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); in opteed_cpu_off_handler()
69 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); in opteed_cpu_suspend_handler()
86 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_SUSPEND); in opteed_cpu_suspend_handler()
103 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_OFF); in opteed_cpu_on_finish_handler()
123 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); in opteed_cpu_on_finish_handler()
138 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_SUSPEND); in opteed_cpu_suspend_finish_handler()
155 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); in opteed_cpu_suspend_finish_handler()
177 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); in opteed_system_off()
197 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); in opteed_system_reset()
/trusted-firmware-a/include/plat/arm/css/common/
A Dcss_pm.h16 #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] argument
17 #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] argument
19 static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) in css_system_pwr_state() argument
22 return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; in css_system_pwr_state()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/include/
A Dmce_private.h89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
115 uint32_t state);
121 uint32_t state,
136 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
146 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
222 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
227 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state);
228 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
230 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
245 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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/trusted-firmware-a/services/std_svc/spm_mm/
A Dspm_mm_main.c35 void sp_state_set(sp_context_t *sp_ptr, sp_state_t state) in sp_state_set() argument
38 sp_ptr->state = state; in sp_state_set()
53 if (sp_ptr->state == from) { in sp_state_wait_switch()
54 sp_ptr->state = to; in sp_state_wait_switch()
73 if (sp_ptr->state == from) { in sp_state_try_switch()
74 sp_ptr->state = to; in sp_state_try_switch()
144 ctx->state = SP_STATE_RESET; in spm_init()
149 ctx->state = SP_STATE_IDLE; in spm_init()
207 assert(sp_ptr->state == SP_STATE_BUSY); in spm_mm_sp_call()
306 if (sp_ctx.state != SP_STATE_RESET) { in spm_mm_smc_handler()
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