| /trusted-firmware-a/plat/qti/qtiseclib/src/ |
| A D | qtiseclib_interface_stub.c | 91 void qtiseclib_psci_node_on_finish(const uint8_t *states) in qtiseclib_psci_node_on_finish() argument
99 void qtiseclib_psci_node_power_off(const uint8_t *states) in qtiseclib_psci_node_power_off() argument
103 void qtiseclib_psci_node_suspend(const uint8_t *states) in qtiseclib_psci_node_suspend() argument
107 void qtiseclib_psci_node_suspend_finish(const uint8_t *states) in qtiseclib_psci_node_suspend_finish() argument
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| /trusted-firmware-a/plat/qti/qtiseclib/inc/ |
| A D | qtiseclib_interface.h | 92 void qtiseclib_psci_node_on_finish(const uint8_t *states);
94 void qtiseclib_psci_node_power_off(const uint8_t *states);
95 void qtiseclib_psci_node_suspend(const uint8_t *states);
96 void qtiseclib_psci_node_suspend_finish(const uint8_t *states);
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
| A D | plat_psci_handlers.c | 184 static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, in tegra_last_on_cpu_in_cluster() argument
192 target = states[pos]; in tegra_last_on_cpu_in_cluster()
206 static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, in tegra_get_afflvl1_pwr_state() argument
210 plat_local_state_t target = states[core_pos]; in tegra_get_afflvl1_pwr_state()
217 if (tegra_last_on_cpu_in_cluster(states, ncpu)) { in tegra_get_afflvl1_pwr_state()
243 const plat_local_state_t *states, in tegra_soc_get_target_pwr_state() argument
250 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
256 target = tegra_get_afflvl1_pwr_state(states, ncpu); in tegra_soc_get_target_pwr_state()
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t186/ |
| A D | plat_psci_handlers.c | 175 static bool tegra_last_cpu_in_cluster(const plat_local_state_t *states, in tegra_last_cpu_in_cluster() argument
183 target = states[pos]; in tegra_last_cpu_in_cluster()
197 static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, in tegra_get_afflvl1_pwr_state() argument
203 plat_local_state_t target = states[core_pos]; in tegra_get_afflvl1_pwr_state()
226 if (tegra_last_cpu_in_cluster(states, ncpu)) { in tegra_get_afflvl1_pwr_state()
258 const plat_local_state_t *states, in tegra_soc_get_target_pwr_state() argument
266 (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
272 target = tegra_get_afflvl1_pwr_state(states, ncpu); in tegra_soc_get_target_pwr_state()
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| /trusted-firmware-a/fdts/ |
| A D | tc.dts | 61 idle-states {
113 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
161 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
185 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
197 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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| A D | fvp-foundation-gicv2-psci.dts | 55 idle-states {
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| A D | fvp-foundation-gicv3-psci.dts | 55 idle-states {
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| A D | fvp-base-gicv2-psci.dts | 54 idle-states {
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| A D | fvp-base-gicv2-psci-aarch32.dts | 55 idle-states {
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| A D | fvp-base-gicv3-psci-aarch32-common.dtsi | 47 idle-states {
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| A D | fvp-defs-dynamiq.dtsi | 36 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
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| A D | fvp-base-gicv3-psci-common.dtsi | 111 idle-states {
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| /trusted-firmware-a/plat/common/ |
| A D | plat_psci_common.c | 149 const plat_local_state_t *states, in plat_get_target_pwr_state() argument
153 const plat_local_state_t *st = states; in plat_get_target_pwr_state()
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| /trusted-firmware-a/plat/nvidia/tegra/common/ |
| A D | tegra_pm.c | 325 const plat_local_state_t *states, in plat_get_target_pwr_state() argument
328 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); in plat_get_target_pwr_state()
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t210/ |
| A D | plat_psci_handlers.c | 102 const plat_local_state_t *states, in tegra_soc_get_target_pwr_state() argument
113 target = *(states + core_pos); in tegra_soc_get_target_pwr_state()
115 target = *(states + cpu); in tegra_soc_get_target_pwr_state()
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| /trusted-firmware-a/plat/nvidia/tegra/include/ |
| A D | tegra_private.h | 119 const plat_local_state_t *states,
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| /trusted-firmware-a/plat/mediatek/mt8173/ |
| A D | plat_pm.c | 589 const plat_local_state_t *states, in plat_get_target_pwr_state() argument
597 temp = *states++; in plat_get_target_pwr_state()
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| /trusted-firmware-a/include/plat/common/ |
| A D | platform.h | 292 const plat_local_state_t *states,
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| /trusted-firmware-a/ |
| A D | readme.rst | 8 or AArch64 execution states.
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| /trusted-firmware-a/docs/components/ |
| A D | granule-protection-tables-design.rst | 11 Arm CCA adds two new security states for a total of four: root, realm, secure, and
12 non-secure. In addition to new security states, corresponding physical address
16 .. list-table:: Security states and PAS access rights
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | granule-protection-tables-design.rst.txt | 11 Arm CCA adds two new security states for a total of four: root, realm, secure, and
12 non-secure. In addition to new security states, corresponding physical address
16 .. list-table:: Security states and PAS access rights
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | index.rst.txt | 40 states.
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| /trusted-firmware-a/docs/ |
| A D | index.rst | 40 states.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/perf/ |
| A D | psci-performance-juno.rst.txt | 25 Juno supports CPU, cluster and system power down states, corresponding to power
26 levels 0, 1 and 2 respectively. It does not support any retention states.
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| /trusted-firmware-a/docs/perf/ |
| A D | psci-performance-juno.rst | 25 Juno supports CPU, cluster and system power down states, corresponding to power
26 levels 0, 1 and 2 respectively. It does not support any retention states.
|