1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PMIC_WRAP_INIT_H 8 #define PMIC_WRAP_INIT_H 9 10 #include <platform_def.h> 11 12 /* external API */ 13 int32_t pwrap_read(uint32_t adr, uint32_t *rdata); 14 int32_t pwrap_write(uint32_t adr, uint32_t wdata); 15 16 static struct mt8173_pmic_wrap_regs *const mtk_pwrap = 17 (void *)PMIC_WRAP_BASE; 18 19 /* timeout setting */ 20 enum { 21 TIMEOUT_RESET = 50, /* us */ 22 TIMEOUT_READ = 50, /* us */ 23 TIMEOUT_WAIT_IDLE = 50 /* us */ 24 }; 25 26 /* PMIC_WRAP registers */ 27 struct mt8173_pmic_wrap_regs { 28 uint32_t mux_sel; 29 uint32_t wrap_en; 30 uint32_t dio_en; 31 uint32_t sidly; 32 uint32_t rddmy; 33 uint32_t si_ck_con; 34 uint32_t cshext_write; 35 uint32_t cshext_read; 36 uint32_t cslext_start; 37 uint32_t cslext_end; 38 uint32_t staupd_prd; 39 uint32_t staupd_grpen; 40 uint32_t reserved[4]; 41 uint32_t staupd_man_trig; 42 uint32_t staupd_sta; 43 uint32_t wrap_sta; 44 uint32_t harb_init; 45 uint32_t harb_hprio; 46 uint32_t hiprio_arb_en; 47 uint32_t harb_sta0; 48 uint32_t harb_sta1; 49 uint32_t man_en; 50 uint32_t man_cmd; 51 uint32_t man_rdata; 52 uint32_t man_vldclr; 53 uint32_t wacs0_en; 54 uint32_t init_done0; 55 uint32_t wacs0_cmd; 56 uint32_t wacs0_rdata; 57 uint32_t wacs0_vldclr; 58 uint32_t wacs1_en; 59 uint32_t init_done1; 60 uint32_t wacs1_cmd; 61 uint32_t wacs1_rdata; 62 uint32_t wacs1_vldclr; 63 uint32_t wacs2_en; 64 uint32_t init_done2; 65 uint32_t wacs2_cmd; 66 uint32_t wacs2_rdata; 67 uint32_t wacs2_vldclr; 68 uint32_t int_en; 69 uint32_t int_flg_raw; 70 uint32_t int_flg; 71 uint32_t int_clr; 72 uint32_t sig_adr; 73 uint32_t sig_mode; 74 uint32_t sig_value; 75 uint32_t sig_errval; 76 uint32_t crc_en; 77 uint32_t timer_en; 78 uint32_t timer_sta; 79 uint32_t wdt_unit; 80 uint32_t wdt_src_en; 81 uint32_t wdt_flg; 82 uint32_t debug_int_sel; 83 uint32_t dvfs_adr0; 84 uint32_t dvfs_wdata0; 85 uint32_t dvfs_adr1; 86 uint32_t dvfs_wdata1; 87 uint32_t dvfs_adr2; 88 uint32_t dvfs_wdata2; 89 uint32_t dvfs_adr3; 90 uint32_t dvfs_wdata3; 91 uint32_t dvfs_adr4; 92 uint32_t dvfs_wdata4; 93 uint32_t dvfs_adr5; 94 uint32_t dvfs_wdata5; 95 uint32_t dvfs_adr6; 96 uint32_t dvfs_wdata6; 97 uint32_t dvfs_adr7; 98 uint32_t dvfs_wdata7; 99 uint32_t spminf_sta; 100 uint32_t cipher_key_sel; 101 uint32_t cipher_iv_sel; 102 uint32_t cipher_en; 103 uint32_t cipher_rdy; 104 uint32_t cipher_mode; 105 uint32_t cipher_swrst; 106 uint32_t dcm_en; 107 uint32_t dcm_dbc_prd; 108 }; 109 110 enum { 111 RDATA_WACS_RDATA_SHIFT = 0, 112 RDATA_WACS_FSM_SHIFT = 16, 113 RDATA_WACS_REQ_SHIFT = 19, 114 RDATA_SYNC_IDLE_SHIFT, 115 RDATA_INIT_DONE_SHIFT, 116 RDATA_SYS_IDLE_SHIFT, 117 }; 118 119 enum { 120 RDATA_WACS_RDATA_MASK = 0xffff, 121 RDATA_WACS_FSM_MASK = 0x7, 122 RDATA_WACS_REQ_MASK = 0x1, 123 RDATA_SYNC_IDLE_MASK = 0x1, 124 RDATA_INIT_DONE_MASK = 0x1, 125 RDATA_SYS_IDLE_MASK = 0x1, 126 }; 127 128 /* WACS_FSM */ 129 enum { 130 WACS_FSM_IDLE = 0x00, 131 WACS_FSM_REQ = 0x02, 132 WACS_FSM_WFDLE = 0x04, 133 WACS_FSM_WFVLDCLR = 0x06, 134 WACS_INIT_DONE = 0x01, 135 WACS_SYNC_IDLE = 0x01, 136 WACS_SYNC_BUSY = 0x00 137 }; 138 139 /* error information flag */ 140 enum { 141 E_PWR_INVALID_ARG = 1, 142 E_PWR_INVALID_RW = 2, 143 E_PWR_INVALID_ADDR = 3, 144 E_PWR_INVALID_WDAT = 4, 145 E_PWR_INVALID_OP_MANUAL = 5, 146 E_PWR_NOT_IDLE_STATE = 6, 147 E_PWR_NOT_INIT_DONE = 7, 148 E_PWR_NOT_INIT_DONE_READ = 8, 149 E_PWR_WAIT_IDLE_TIMEOUT = 9, 150 E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, 151 E_PWR_INIT_SIDLY_FAIL = 11, 152 E_PWR_RESET_TIMEOUT = 12, 153 E_PWR_TIMEOUT = 13, 154 E_PWR_INIT_RESET_SPI = 20, 155 E_PWR_INIT_SIDLY = 21, 156 E_PWR_INIT_REG_CLOCK = 22, 157 E_PWR_INIT_ENABLE_PMIC = 23, 158 E_PWR_INIT_DIO = 24, 159 E_PWR_INIT_CIPHER = 25, 160 E_PWR_INIT_WRITE_TEST = 26, 161 E_PWR_INIT_ENABLE_CRC = 27, 162 E_PWR_INIT_ENABLE_DEWRAP = 28, 163 E_PWR_INIT_ENABLE_EVENT = 29, 164 E_PWR_READ_TEST_FAIL = 30, 165 E_PWR_WRITE_TEST_FAIL = 31, 166 E_PWR_SWITCH_DIO = 32 167 }; 168 169 #endif /* PMIC_WRAP_INIT_H */ 170