Searched refs:up (Results 1 – 25 of 146) sorted by relevance
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| /trusted-firmware-a/docs/resources/diagrams/plantuml/ |
| A D | io_arm_class_diagram.puml | 46 FIP_IMAGE_ID -up-|> plat_io_policy
47 BL2_IMAGE_ID -up-|> plat_io_policy
48 xxx_IMAGE_ID -up-|> plat_io_policy
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| A D | fip-secure-partitions.puml | 141 config.json .up.> SP_vendor_1
142 config.json .up.> SP_vendor_2
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| /trusted-firmware-a/docs/build/TF-A_2.5/_static/css/ |
| A D | badge_only.css | 1 …up:before,.icon-caret-up:before{content:"\f0d8"}.fa-caret-left:before,.icon-caret-left:before{cont…
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| /trusted-firmware-a/docs/plat/ |
| A D | mt8195.rst | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| A D | mt8192.rst | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2 GHz.
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| A D | mt8183.rst | 6 Both clusters can operate at up to 2 GHz.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | mt8192.rst.txt | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2 GHz.
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| A D | mt8195.rst.txt | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| A D | mt8183.rst.txt | 6 Both clusters can operate at up to 2 GHz.
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| A D | ls1043a.rst.txt | 34 UART: supports two UARTs up to 115200 bps for console
84 Then change to Alt bank and boot up TF-A:
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| /trusted-firmware-a/fdts/ |
| A D | stm32mp15-pinctrl.dtsi | 30 bias-pull-up;
65 bias-pull-up;
83 bias-pull-up;
115 bias-pull-up;
119 bias-pull-up;
132 bias-pull-up;
138 bias-pull-up;
169 bias-pull-up;
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| A D | stm32mp157c-lxa-mc1.dts | 68 bias-pull-up;
72 bias-pull-up;
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| A D | fvp-base-gicv3-psci.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs */
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| A D | fvp-base-gicv3-psci-aarch32.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs */
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| A D | fvp-base-gicv3-psci-1t.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
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| A D | fvp-base-gicv3-psci-aarch32-1t.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
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| A D | fvp-base-gicv3-psci-dynamiq.dts | 7 /* DynamIQ configuration: 1 cluster with up to 8 CPUs */
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| A D | fvp-base-gicv3-psci-dynamiq-2t.dts | 7 /* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
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| /trusted-firmware-a/plat/nxp/common/fip_handler/fuse_fip/ |
| A D | fuse.mk | 49 FUSE_FIP_ARGS += --fuse-up ${BUILD_PLAT}/${FUSE_UP_FILE_SB}
52 FUSE_FIP_ARGS += --fuse-up ${FUSE_UP_FILE}
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| /trusted-firmware-a/docs/build/latex/ |
| A D | sphinxlatexindbibtoc.sty | 6 % Provides support for this output mark-up from Sphinx latex writer:
10 % - sphinxtheindex (direct mark-up or via python.ist or sphinx.xdy)
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| /trusted-firmware-a/docs/plat/nxp/ |
| A D | index.rst | 13 It includes details on image flashing, fuse provisioning and trusted board boot-up.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/nxp/ |
| A D | index.rst.txt | 13 It includes details on image flashing, fuse provisioning and trusted board boot-up.
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| /trusted-firmware-a/drivers/renesas/common/ddr/ddr_b/ |
| A D | boot_init_dram_config.c | 1890 uint32_t dataL, down, up; in opencheck_SSI_WS6() local
1924 up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; in opencheck_SSI_WS6()
1932 if (down == up) { in opencheck_SSI_WS6()
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| /trusted-firmware-a/docs/process/ |
| A D | faq.rst | 33 bug-fixes but may wait up to a week to merge major changes, or ones requiring
50 several things over the course of a few days, it might take up to a week.
58 1-2 days later. This whole process could take up 4 weeks. Please refer to the
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/process/ |
| A D | faq.rst.txt | 33 bug-fixes but may wait up to a week to merge major changes, or ones requiring
50 several things over the course of a few days, it might take up to a week.
58 1-2 days later. This whole process could take up 4 weeks. Please refer to the
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