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Searched refs:win_reg (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a/drivers/marvell/
A Diob.c168 uint32_t win_id, win_reg; in init_iob() local
191 win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); in init_iob()
192 win_reg &= ~WIN_ENABLE_BIT; in init_iob()
193 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg); in init_iob()
195 win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE; in init_iob()
196 win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE; in init_iob()
197 win_reg &= ~IOB_WIN_ENA_WRITE_SECURE; in init_iob()
198 win_reg &= ~IOB_WIN_ENA_READ_SECURE; in init_iob()
199 mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg); in init_iob()
A Dgwin.c95 uint32_t win_reg; in gwin_disable_window() local
97 win_reg = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_num)); in gwin_disable_window()
98 win_reg &= ~WIN_ENABLE_BIT; in gwin_disable_window()
99 mmio_write_32(GWIN_CR_OFFSET(ap_index, win_num), win_reg); in gwin_disable_window()
185 uint32_t win_reg; in init_gwin() local
220 win_reg = mmio_read_32(CCU_GRU_CR_OFFSET(ap_index)); in init_gwin()
221 win_reg |= CCR_GRU_CR_GWIN_MBYPASS; in init_gwin()
222 mmio_write_32(CCU_GRU_CR_OFFSET(ap_index), win_reg); in init_gwin()
A Dio_win.c95 uint32_t win_reg; in io_win_disable_window() local
102 win_reg = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_num)); in io_win_disable_window()
103 win_reg &= ~WIN_ENABLE_BIT; in io_win_disable_window()
104 mmio_write_32(IO_WIN_ALR_OFFSET(ap_index, win_num), win_reg); in io_win_disable_window()
231 uint32_t win_id, win_reg; in init_io_win() local
248 win_reg = marvell_get_io_win_gcr_target(ap_index); in init_io_win()
250 win_reg); in init_io_win()
A Dccu.c149 uint32_t win_reg; in ccu_disable_win() local
156 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in ccu_disable_win()
157 win_reg &= ~WIN_ENABLE_BIT; in ccu_disable_win()
158 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); in ccu_disable_win()
320 uint32_t win_id, win_reg; in init_ccu() local
351 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; in init_ccu()
352 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); in init_ccu()
390 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) in init_ccu()
392 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); in init_ccu()
A Damb_adec.c122 uint32_t win_id, win_reg; in init_amb_adec() local
142 win_reg = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in init_amb_adec()
143 win_reg &= ~WIN_ENABLE_BIT; in init_amb_adec()
144 mmio_write_32(AMB_WIN_CR_OFFSET(win_id), win_reg); in init_amb_adec()

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