1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef DRAM_H
8 #define DRAM_H
9 
10 #include <stdint.h>
11 
12 #include <dram_regs.h>
13 #include <plat_private.h>
14 
15 enum {
16 	DDR3 = 3,
17 	LPDDR2 = 5,
18 	LPDDR3 = 6,
19 	LPDDR4 = 7,
20 	UNUSED = 0xff
21 };
22 
23 struct rk3399_ddr_pctl_regs {
24 	uint32_t denali_ctl[CTL_REG_NUM];
25 };
26 
27 struct rk3399_ddr_publ_regs {
28 	/*
29 	 * PHY registers from 0 to 90 for slice1.
30 	 * These are used to restore slice1-4 on resume.
31 	 */
32 	uint32_t phy0[91];
33 	/*
34 	 * PHY registers from 512 to 895.
35 	 * Only registers 0-37 of each 128 register range are used.
36 	 */
37 	uint32_t phy512[3][38];
38 	uint32_t phy896[63];
39 };
40 
41 struct rk3399_ddr_pi_regs {
42 	uint32_t denali_pi[PI_REG_NUM];
43 };
44 union noc_ddrtiminga0 {
45 	uint32_t d32;
46 	struct {
47 		unsigned acttoact : 6;
48 		unsigned reserved0 : 2;
49 		unsigned rdtomiss : 6;
50 		unsigned reserved1 : 2;
51 		unsigned wrtomiss : 6;
52 		unsigned reserved2 : 2;
53 		unsigned readlatency : 8;
54 	} b;
55 };
56 
57 union noc_ddrtimingb0 {
58 	uint32_t d32;
59 	struct {
60 		unsigned rdtowr : 5;
61 		unsigned reserved0 : 3;
62 		unsigned wrtord : 5;
63 		unsigned reserved1 : 3;
64 		unsigned rrd : 4;
65 		unsigned reserved2 : 4;
66 		unsigned faw : 6;
67 		unsigned reserved3 : 2;
68 	} b;
69 };
70 
71 union noc_ddrtimingc0 {
72 	uint32_t d32;
73 	struct {
74 		unsigned burstpenalty : 4;
75 		unsigned reserved0 : 4;
76 		unsigned wrtomwr : 6;
77 		unsigned reserved1 : 18;
78 	} b;
79 };
80 
81 union noc_devtodev0 {
82 	uint32_t d32;
83 	struct {
84 		unsigned busrdtord : 3;
85 		unsigned reserved0 : 1;
86 		unsigned busrdtowr : 3;
87 		unsigned reserved1 : 1;
88 		unsigned buswrtord : 3;
89 		unsigned reserved2 : 1;
90 		unsigned buswrtowr : 3;
91 		unsigned reserved3 : 17;
92 	} b;
93 };
94 
95 union noc_ddrmode {
96 	uint32_t d32;
97 	struct {
98 		unsigned autoprecharge : 1;
99 		unsigned bypassfiltering : 1;
100 		unsigned fawbank : 1;
101 		unsigned burstsize : 2;
102 		unsigned mwrsize : 2;
103 		unsigned reserved2 : 1;
104 		unsigned forceorder : 8;
105 		unsigned forceorderstate : 8;
106 		unsigned reserved3 : 8;
107 	} b;
108 };
109 
110 struct rk3399_msch_timings {
111 	union noc_ddrtiminga0 ddrtiminga0;
112 	union noc_ddrtimingb0 ddrtimingb0;
113 	union noc_ddrtimingc0 ddrtimingc0;
114 	union noc_devtodev0 devtodev0;
115 	union noc_ddrmode ddrmode;
116 	uint32_t agingx0;
117 };
118 
119 struct rk3399_sdram_channel {
120 	unsigned char rank;
121 	/* col = 0, means this channel is invalid */
122 	unsigned char col;
123 	/* 3:8bank, 2:4bank */
124 	unsigned char bk;
125 	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
126 	unsigned char bw;
127 	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
128 	unsigned char dbw;
129 	/* row_3_4 = 1: 6Gb or 12Gb die
130 	 * row_3_4 = 0: normal die, power of 2
131 	 */
132 	unsigned char row_3_4;
133 	unsigned char cs0_row;
134 	unsigned char cs1_row;
135 	uint32_t ddrconfig;
136 	struct rk3399_msch_timings noc_timings;
137 };
138 
139 struct rk3399_sdram_params {
140 	struct rk3399_sdram_channel ch[2];
141 	uint32_t ddr_freq;
142 	unsigned char dramtype;
143 	unsigned char num_channels;
144 	unsigned char stride;
145 	unsigned char odt;
146 	struct rk3399_ddr_pctl_regs pctl_regs;
147 	struct rk3399_ddr_pi_regs pi_regs;
148 	struct rk3399_ddr_publ_regs phy_regs;
149 	uint32_t rx_cal_dqs[2][4];
150 };
151 
152 extern struct rk3399_sdram_params sdram_config;
153 
154 void dram_init(void);
155 
156 #endif /* DRAM_H */
157