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/trusted-firmware-a/drivers/renesas/rcar/pfc/D3/
A Dpfc_init_d3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/plat/intel/soc/common/drivers/qspi/
A Dcadence_qspi.h25 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
34 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
44 #define CAD_QSPI_DELAY_CSSOT(x) (((x) & 0xff) << 0) argument
45 #define CAD_QSPI_DELAY_CSEOT(x) (((x) & 0xff) << 8) argument
47 #define CAD_QSPI_DELAY_CSDA(x) (((x) & 0xff) << 24) argument
50 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x) ((x) << 0) argument
51 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x) ((x) << 4) argument
52 #define CAD_QSPI_DEVSZ_BYTES_PER_BLOCK(x) ((x) << 16) argument
56 #define CAD_QSPI_DEV_OPCODE(x) (((x) & 0xff) << 0) argument
97 #define CAD_QSPI_SELCLKPHASE(x) (((x) & 1) << 2) argument
[all …]
/trusted-firmware-a/lib/compiler-rt/builtins/
A Dint_math.h41 #define crt_isfinite(x) _finite((x)) argument
42 #define crt_isinf(x) !_finite((x)) argument
43 #define crt_isnan(x) _isnan((x)) argument
54 __typeof((x)) x_ = (x); \
75 #define crt_fabs(x) fabs((x)) argument
76 #define crt_fabsf(x) fabsf((x)) argument
77 #define crt_fabsl(x) fabs((x)) argument
85 #define crt_fmax(x, y) __max((x), (y)) argument
95 #define crt_logb(x) logb((x)) argument
96 #define crt_logbf(x) logbf((x)) argument
[all …]
A Dpopcountsi2.c22 su_int x = (su_int)a; in __popcountsi2() local
23 x = x - ((x >> 1) & 0x55555555); in __popcountsi2()
25 x = ((x >> 2) & 0x33333333) + (x & 0x33333333); in __popcountsi2()
27 x = (x + (x >> 4)) & 0x0F0F0F0F; in __popcountsi2()
29 x = (x + (x >> 16)); in __popcountsi2()
32 return (x + (x >> 8)) & 0x0000003F; /* (6 significant bits) */ in __popcountsi2()
/trusted-firmware-a/drivers/renesas/rcar/pfc/H3/
A Dpfc_init_h3_v1.c166 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
167 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
168 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
169 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
170 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
171 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
172 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
173 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
277 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
278 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
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A Dpfc_init_h3_v2.c168 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
169 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
170 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
171 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
172 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
173 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
174 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
175 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
279 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
280 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/drivers/renesas/rcar/pfc/M3N/
A Dpfc_init_m3n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/drivers/renesas/rzg/pfc/G2H/
A Dpfc_init_g2h.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/drivers/renesas/rzg/pfc/G2N/
A Dpfc_init_g2n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/drivers/renesas/rcar/pfc/M3/
A Dpfc_init_m3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/drivers/renesas/rzg/pfc/G2M/
A Dpfc_init_g2m.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/trusted-firmware-a/include/lib/libc/aarch32/
A Dendian_.h68 #define __ntohl(x) ((uint32_t)(x)) argument
69 #define __ntohs(x) ((uint16_t)(x)) argument
70 #define __htonl(x) ((uint32_t)(x)) argument
71 #define __htons(x) ((uint16_t)(x)) argument
75 #define __ntohl(x) (__bswap32(x)) argument
76 #define __ntohs(x) (__bswap16(x)) argument
77 #define __htonl(x) (__bswap32(x)) argument
78 #define __htons(x) (__bswap16(x)) argument
131 #define __bswap16(x) \ argument
142 #define __bswap16(x) __bswap16_var(x) argument
[all …]
/trusted-firmware-a/include/lib/libc/
A Dendian.h45 #define bswap16(x) __bswap16(x) argument
46 #define bswap32(x) __bswap32(x) argument
47 #define bswap64(x) __bswap64(x) argument
54 #define htobe16(x) bswap16((x)) argument
55 #define htobe32(x) bswap32((x)) argument
56 #define htobe64(x) bswap64((x)) argument
61 #define be16toh(x) bswap16((x)) argument
62 #define be32toh(x) bswap32((x)) argument
63 #define be64toh(x) bswap64((x)) argument
71 #define htole16(x) bswap16((x)) argument
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/trusted-firmware-a/plat/intel/soc/agilex/include/
A Dagilex_memory_controller.h23 #define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
38 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
39 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
40 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
41 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) argument
42 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
44 #define AGX_MPFE_DDR(x) (0xf8000000 + x) argument
65 #define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
69 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
99 #define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x3) >> 0) argument
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A Dagilex_clock_manager.h80 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) argument
81 #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) argument
82 #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) argument
93 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) argument
99 #define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) argument
107 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) argument
111 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
112 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) argument
113 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) argument
115 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) argument
[all …]
/trusted-firmware-a/plat/intel/soc/stratix10/include/
A Ds10_memory_controller.h21 #define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
37 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
38 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
39 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
40 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) argument
41 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
43 #define S10_MPFE_DDR(x) (0xf8000000 + x) argument
56 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) argument
64 #define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
68 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
[all …]
A Ds10_clock_manager.h22 #define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) argument
23 #define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) argument
24 #define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9) argument
46 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) argument
48 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
50 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff) argument
51 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) argument
53 #define ALT_CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) argument
79 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) argument
82 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
[all …]
/trusted-firmware-a/include/lib/libc/aarch64/
A Dendian_.h63 #define __ntohl(x) (__bswap32(x)) argument
64 #define __ntohs(x) (__bswap16(x)) argument
65 #define __htonl(x) (__bswap32(x)) argument
66 #define __htons(x) (__bswap16(x)) argument
69 __bswap64(uint64_t x) in __bswap64() argument
113 #define __bswap16(x) \ argument
116 __bswap16_var(x)))
118 #define __bswap32(x) \ argument
121 __bswap32_var(x)))
124 #define __bswap16(x) __bswap16_var(x) argument
[all …]
/trusted-firmware-a/include/lib/libfdt/
A Dlibfdt_env.h29 #define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) argument
30 #define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) argument
31 #define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ argument
32 (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3))
33 #define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ argument
34 (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \
35 (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \
36 (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7))
44 return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x); in cpu_to_fdt16()
53 return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x); in cpu_to_fdt32()
[all …]
/trusted-firmware-a/drivers/nxp/flexspi/nor/
A Dfspi.h163 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) argument
164 #define FSPI_MCR0_END_CFG(x) ((x) << 2) argument
183 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) argument
276 #define FSPI_FLSHXCR1_TCSS(x) (x) argument
300 #define FSPI_IPCR1_IDATSZ(x) (x) argument
333 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) argument
347 #define FSPI_STS0_DLPHB(x) ((x) << 8) argument
348 #define FSPI_STS0_DLPHA(x) ((x) << 4) argument
357 #define FSPI_STS1_AHB_ERRID(x) (x) argument
366 #define FSPI_IPRXFSTS_FILL(x) (x) argument
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/trusted-firmware-a/plat/nvidia/tegra/soc/t210/drivers/se/
A Dse_private.h53 #define SE_STATUS(x) \ argument
59 #define SE_MEM_INTERFACE(x) ((x) << SE_STATUS_SHIFT) argument
65 #define SE_SECURITY_TZ_LOCK_SOFT(x) ((x) << SE_SECURITY_TZ_LOCK_SOFT_SHIFT) argument
70 #define SE_SEC_ENG_DISABLE(x)((x) << SE_SEC_ENG_DIS_SHIFT) argument
107 #define SE_CONFIG_DST(x) \ argument
251 #define SE_CRYPTO_KEY_INDEX(x) (x << SE_CRYPTO_KEY_INDEX_SHIFT) argument
264 #define SE_KEYTABLE_SLOT(x) (x << SE_KEYTABLE_SLOT_SHIFT) argument
303 #define SE_OPERATION(x) \ argument
321 #define SE_CTX_SAVE_KEY_INDEX(x) (x << SE_CTX_SAVE_KEY_INDEX_SHIFT) argument
352 #define SE_CTX_STICKY_WORD_QUAD(x) (x << SE_CTX_STICKY_WORD_QUAD_SHIFT) argument
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/trusted-firmware-a/include/drivers/brcm/
A Dchimp_nv_defs.h48 SIZEOF_IN_BITS(x) == 32 ? BYTE_SWAP_32(x) : (x))
55 #define BE_INT16(x) (x) argument
56 #define BE_INT32(x) (x) argument
57 #define BE_INT(x) (x) argument
58 #define LE_INT16(x) BYTE_SWAP_16(x) argument
59 #define LE_INT32(x) BYTE_SWAP_32(x) argument
60 #define LE_INT(x) BYTE_SWAP_INT(x) argument
64 #define LE_INT16(x) (x) argument
65 #define LE_INT32(x) (x) argument
66 #define LE_INT(x) (x) argument
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/trusted-firmware-a/plat/intel/soc/common/drivers/ccu/
A Dncore_ccu.h77 #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ argument
78 + NCORE_DIRU_SIZE * (x))
80 + NCORE_CAIU_SIZE * (x))
85 #define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24) argument
86 #define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16) argument
87 #define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8) argument
88 #define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0) argument
90 #define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18) argument
92 #define SNOOP_FILTER_ID(x) (((x) << 16)) argument
94 #define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) argument
[all …]
/trusted-firmware-a/include/export/common/
A Dep_info_exp.h50 #define EP_GET_EE(x) ((x) & EP_EE_MASK) argument
51 #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) argument
58 #define EP_GET_ST(x) ((x) & EP_ST_MASK) argument
59 #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) argument
66 #define EP_GET_EXE(x) ((x) & EP_EXE_MASK) argument
67 #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) argument
73 #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) argument
74 #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) argument
/trusted-firmware-a/plat/hisilicon/hikey960/include/
A Dhi3660_crg.h84 #define SC_DIV_LPMCU(x) (((x) & 0x1F) << 5) argument
100 #define SC_DIV_A53HPM(x) (((x) & 0x7) << 13) argument
104 #define DDRC_CLK_SW_REQ_CFG(x) (((x) & 0x3) << 12) argument
106 #define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9) argument
125 #define DIV_CLK_DDRSYS(x) (((x) & 0x3) << 10) argument
128 #define DIV_CLK_DDRCFG(x) (((x) & 0x6) << 5) argument
131 #define DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK) argument
132 #define GET_DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK) argument
136 #define DIV_SYSBUS_PLL(x) ((x) & 0xF) argument
140 #define PERI_TIME_STAMP_CLK_DIV(x) (((x) & 0x7) << 22) argument
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