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/trusted-firmware-a/lib/cpus/aarch64/
A D	cortex_a77.S	38 cbz x0, 3f 43 cbz x0, 1f 44 ldr x0, =0x0 52 ldr x0, =0x1 60 ldr x0, =0x0 100 cbz x0, 1f 129 cbz x0, 1f 131 ldr x0,=0x4 140 ldr x0,=0x5 180 cbz x0, 1f [all …]
A D	cortex_a78.S	32 cbz x0, 1f 58 cbz x0, 1f 89 cbz x0, 1f 99 mov x0, #1 108 mov x0, #2 140 cbz x0, 1f 168 cbz x0, 1f 213 cbz x0, 1f 243 cbz x0, 1f 313 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT [all …]
A D	cortex_a78_ae.S	32 cbz x0, 1f 36 bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 62 cbz x0, 1f 72 mov x0, #1 81 mov x0, #2 109 mov x18, x0 112 mov x0, x18 117 mov x0, x18 124 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 129 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT [all …]
A D	neoverse_n2.S	34 cbz x0, 1f 37 ldr x0,=0x6 45 ldr x0,=0x7 76 cbz x0, 1f 156 cbz x0, 1f 198 cbz x0, 1f 353 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 405 orr x0, x0, #TAM_BIT 410 orr x0, x0, #TAM_BIT 419 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT [all …]
A D	neoverse_v1.S	35 cbz x0, 1f 63 cbz x0, 1f 91 cbz x0, 1f 119 cbz x0, 1f 150 cbz x0, 1f 152 mov x0, #0 161 mov x0, #1 170 mov x0, #2 204 cbz x0, 1f 239 cbz x0, 1f [all …]
A D	cortex_a710.S	37 cbz x0, 1f 40 ldr x0,=0x6 48 ldr x0,=0x7 80 cbz x0, 1f 83 ldr x0,=0x3 91 ldr x0,=0x4 122 cbz x0, 1f 176 cbz x0, 1f 204 cbz x0, 1f 243 mov x8, x0 [all …]
A D	neoverse_n1.S	38 cbz x0, 1f 41 ldr x0, =0x0 92 cbz x0, 1f 118 cbz x0, 1f 144 cbz x0, 1f 171 cbz x0, 1f 330 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 474 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 554 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 559 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT [all …]
A D	cortex_a72.S	31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 34 bic x0, x0, x1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 69 mov x0, #1 87 cbz x0, 1f 143 mov x18, x0 146 mov x0, x18 160 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 171 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT [all …]
A D	cortex_a75.S	32 cbz x0, 1f 60 cbz x0, 1f 81 mov x18, x0 84 mov x0, x18 89 mov x0, x18 96 msr vbar_el3, x0 103 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 119 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 125 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 174 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK [all …]
A D	cpu_helpers.S	34 cmp x0, #0 67 cmp x0, x2 73 cmp x0, #0 103 cmp x0, #0 126 cbz x0, 1f 168 mov x0, #0 374 ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR] 379 ldr x0, [x0, #CPU_EXTRA1_FUNC] 386 br x0 411 ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR] [all …]
A D	rainier.S	33 mrs x0, id_aa64pfr1_el1 51 orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2 56 mov x18, x0 60 mrs x0, actlr_el3 61 orr x0, x0, #RAINIER_ACTLR_AMEN_BIT 62 msr actlr_el3, x0 65 mrs x0, actlr_el2 66 orr x0, x0, #RAINIER_ACTLR_AMEN_BIT 67 msr actlr_el2, x0 88 orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK [all …]
A D	cortex_a55.S	33 cbz x0, 1f 63 cbz x0, 1f 86 csel x0, x0, x2, eq 104 cbz x0, 1f 136 cbz x0, 1f 164 cbz x0, 1f 192 cbz x0, 1f 251 mov x18, x0 254 mov x0, x18 296 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK [all …]
A D	cortex_a76.S	53 cmp x0, x2 78 mov x0, xzr 214 cbz x0, 1f 242 cbz x0, 1f 270 cbz x0, 1f 298 cbz x0, 1f 326 cbz x0, 1f 575 lsr x0, x0, #ID_AA64PFR1_EL1_SSBS_SHIFT 576 and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK 578 cmp x0, 0 [all …]
/trusted-firmware-a/plat/nvidia/tegra/common/aarch64/
A D	tegra_helpers.S	66 and x0, x0, x1 67 lsr x0, x0, #MIDR_PN_SHIFT 78 orr x0, x0, x1 85 orr x0, x0, x1 95 orr x0, x0, x1 99 orr x0, x0, x1 110 lsl x0, x1, x0 123 orr x0, x0, #EL0VCTEN_BIT 326 orr x0, x0, #1 335 bic x0, x0, #1 [all …]
/trusted-firmware-a/include/arch/aarch64/
A D	el3_common_macros.S	38 orr x0, x0, x1 89 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 96 orr x0, x0, #SCR_EEL2_BIT 159 orr x0, x0, #MDCR_TTRF_BIT 234 orr x0, x0, #TTA_BIT 363 and x0, x0, #~(PAGE_SIZE_MASK) 445 add x0, x0, :lo12:__TEXT_START__ 448 add x0, x0, :lo12:__RO_START__ 452 add x0, x0, :lo12:__RW_START__ 460 add x0, x0, :lo12:__NOBITS_START__ [all …]
A D	el2_common_macros.S	40 mrs x0, sctlr_el2 41 orr x0, x0, x1 42 msr sctlr_el2, x0 77 orr x0, x0, #(HCR_API_BIT | HCR_APK_BIT) 79 msr hcr_el2, x0 159 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 163 msr DIT, x0 261 br x0 279 and x0, x0, #~(PAGE_SIZE_MASK) 343 add x0, x0, :lo12:__BSS_START__ [all …]
/trusted-firmware-a/plat/rpi/common/aarch64/
A D	plat_helpers.S	45 and x0, x0, #MPIDR_CLUSTER_MASK 46 add x0, x1, x0, LSR #6 59 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 80 lsl x0, x0, #3 82 add x0, x0, x2 89 str x1,[x0] 94 ldr x1, [x0] 100 ldr x1, [x0] 140 ldr x0, [x0] 143 csel x0, x0, xzr, eq [all …]
/trusted-firmware-a/plat/layerscape/board/ls1043/aarch64/
A D	ls1043_helpers.S	16 mrs x0, mpidr_el1 18 and x0, x0, #MPIDR_CLUSTER_MASK 19 add x0, x1, x0, LSR #4 //4 cores 30 str w1, [x0, #0x110] 33 str w1, [x0, #0x000] 36 str w1, [x0, #0x080] 39 str w1, [x0, #0x104] 42 str w1, [x0, #0x108] 45 str w1, [x0, #0x10C] 48 str w1, [x0, #0x100] [all …]
/trusted-firmware-a/bl32/tsp/aarch64/
A D	tsp_entrypoint.S	31 ldp x0, x1, [x0, #TSP_ARG0] 63 and x0, x0, #~(PAGE_SIZE_MASK) 92 orr x0, x0, x1 93 bic x0, x0, #SCTLR_DSSBS_BIT 113 add x0, x0, :lo12:__TEXT_START__ 116 add x0, x0, :lo12:__RO_START__ 120 add x0, x0, :lo12:__RW_START__ 134 add x0, x0, :lo12:__BSS_START__ 142 add x0, x0, :lo12:__COHERENT_RAM_START__ 193 mov x1, x0 [all …]
/trusted-firmware-a/plat/marvell/armada/common/aarch64/
A D	marvell_helpers.S	53 and x0, x0, #MPIDR_CLUSTER_MASK 54 add x0, x1, x0, LSR #7 71 mul x1, x0, x1 133 bic x0, x0, 0x1 /* M bit - MMU */ 134 bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */ 159 bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */ 198 str w1, [x0] 217 mov x28, x0 245 mov x0, x28 246 br x0 [all …]
/trusted-firmware-a/lib/extensions/mtpmu/aarch64/
A D	mtpmu.S	30 and x0, x1, x0, LSR #ID_AA64DFR0_MTPMU_SHIFT 32 cset x0, eq 46 lsr x1, x1, x0 48 cset x0, eq 67 cbz x0, 1f 70 mrs x0, mdcr_el3 72 bic x0, x0, x1 73 msr mdcr_el3, x0 90 mrs x0, mdcr_el2 92 bic x0, x0, x1 [all …]
/trusted-firmware-a/plat/imx/common/
A D	imx8_helpers.S	32 mrs x0, midr_el1 33 ubfx x0, x0, MIDR_PN_SHIFT, #12 56 mrs x0, mpidr_el1 57 and x0, x0, #(MPIDR_CPU_MASK) 59 cset x0, eq 72 and x0, x0, #MPIDR_CLUSTER_MASK 73 add x0, x1, x0, LSR #6 84 and x0, x0, #MPIDR_CLUSTER_MASK 85 add x0, x1, x0, LSR #6 110 mov x0, #1 [all …]
/trusted-firmware-a/plat/brcm/board/stingray/aarch64/
A D	plat_helpers.S	46 orr x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI 48 bic x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI 60 bic x0, x0, x1 65 orr x0, x0, x1 100 mov x0, #0 116 add x0, x1, x0, LSL #3 118 str x1, [x0] 122 ldr x1, [x0] 150 mov x0, xzr 255 and x0, x0, #MPIDR_CLUSTER_MASK [all …]
/trusted-firmware-a/lib/el3_runtime/aarch64/
A D	context.S	60 str x15, [x0, #CTX_CPTR_EL2] 93 str x13, [x0, #CTX_PMSCR_EL2] 96 str x14, [x0, #CTX_SCTLR_EL2] 120 str x9, [x0, #CTX_TFSR_EL2] 293 ldr x9, [x0, #CTX_TFSR_EL2] 782 msr APIAKeyLo_EL1, x0 800 mrs x0, scr_el3 801 tst x0, #SCR_NS_BIT 812 mrs x0, mdcr_el3 813 tst x0, x1 [all …]
/trusted-firmware-a/plat/arm/css/sgi/aarch64/
A D	sgi_helper.S	38 mov x4, x0 57 madd x0, x1, x4, x0 80 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 81 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 82 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 87 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 88 bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 89 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 94 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 95 bic x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT [all …]

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