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/trusted-firmware-a/plat/common/aarch64/
A D	crash_console_helpers.S	71 mrs x1, sctlr_el3 81 add x1, x1, :lo12:crash_console_triggered 82 ldarb w2, [x1] 87 stlrb w3, [x1] 112 add x1, x1, :lo12:crash_console_reg_stash 113 stp x14, x15, [x1] 132 mov x1, x15 137 mov x1, x15 146 add x1, x1, :lo12:crash_console_reg_stash 161 add x1, x1, :lo12:crash_console_reg_stash [all …]
/trusted-firmware-a/lib/cpus/aarch64/
A D	cortex_a57.S	21 mrs x1, sctlr_el3 22 bic x1, x1, #SCTLR_C_BIT 36 orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK 37 bic x0, x0, x1 90 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 97 mov x1, #0x00 132 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI 204 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD 231 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB 258 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE [all …]
A D	cortex_a55.S	35 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 43 mov x1, #0x00 65 orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL 68 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 77 mov x1, #0x00 83 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 84 cmp x1, #0 106 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 114 mov x1, #0x00 138 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE [all …]
A D	neoverse_n1.S	56 mov x1, #0x10 94 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 120 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 146 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 147 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 173 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 199 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 225 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 251 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 303 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 [all …]
A D	cpu_helpers.S	79 add x1, x1, x2, lsl #3 80 ldr x1, [x0, x1] 82 cmp x1, #0 85 br x1 196 add x1, x1, :lo12:unsupported_mpid_flag 247 cmp x0, x1 263 cmp x0, x1 279 cmp x0, x1 281 cbz x1, 1f 341 ldr x1, [x1, #CPU_ERRATA_PRINTED] [all …]
A D	neoverse_n2.S	60 mov x1, #0x00 78 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 86 mov x1, #0x00 104 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 131 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 182 mov x1, #0x00 202 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 210 mov x1, #0x00 259 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 287 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 [all …]
A D	cortex_a53.S	25 mrs x1, sctlr_el3 26 bic x1, x1, #SCTLR_C_BIT 27 msr sctlr_el3, x1 57 mov x1, #0x01 74 mov x1, #0x02 95 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 96 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 103 mov x1, #0x02 119 mov x1, #0x02 149 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH [all …]
A D	cortex_a76.S	80 csel x1, x1, x0, eq 224 mov x1, #0x10 244 orr x1, x1 ,#(1 << 59) 252 mov x1, #0x20 272 orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 280 mov x1, #0x20 300 orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10 308 mov x1, #0x30 328 orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51 371 orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2 [all …]
A D	denver.S	36 mrs x1, pmcr_el0 167 cmp x1, x2 172 mov x1, #1 173 lsl x1, x1, x0 187 cmp x1, x2 193 mov x1, #1 194 lsl x1, x1, x0 203 and x2, x2, x1 221 and x1, x1, x2 222 cbz x1, 1f [all …]
/trusted-firmware-a/plat/nxp/soc-lx2160a/aarch64/
A D	lx2160a_warm_rst.S	45 ldr x1, =NXP_DDR_ADDR 47 ldr w0, [x1, #SDRAM_CFG] 49 str w0, [x1, #SDRAM_CFG] 51 ldr w0, [x1, #DEBUG_2] 55 ldr w0, [x1, #DEBUG_26] 64 str w0, [x1, #DEBUG_26] 71 ldr w0, [x1, #DDR_DSR2] 73 str w0, [x1, #DDR_DSR2] 74 ldr w0, [x1, #DDR_DSR2] 98 ldr w0, [x1, #DDR_DSR2] [all …]
A D	lx2160a.S	297 lsl x1, x1, #8 330 orr x1, x1, #CPUECTLR_SMPEN_EN 336 bic x1, x1, #CPUECTLR_TIMER_MASK 427 orr x1, x1, #CNTP_CTL_EL0_IMASK 645 orr x1, x1, x2 649 orr x1, x1, x2 741 bic x1, x1, #CPUECTLR_RET_MASK 743 orr x1, x1, #CPUECTLR_SMPEN_EN 923 add x1, x1, #CCN_HNF_OFFSET 1366 bic x1, x1, x2 [all …]
/trusted-firmware-a/include/arch/aarch64/
A D	el3_common_macros.S	158 cbz x1, 1f 233 cbz x1, 1f 365 add x1, x1, x0 455 add x1, x1, :lo12:__RW_END__ 456 sub x1, x1, x0 462 add x1, x1, :lo12:__NOBITS_END__ 463 sub x1, x1, x0 471 add x1, x1, :lo12:__BSS_END__ 472 sub x1, x1, x0 480 sub x1, x1, x0 [all …]
A D	console_macros.S	26 adrp x1, console_\_driver\()_putc 27 add x1, x1, :lo12:console_\_driver\()_putc 28 str x1, [x0, #CONSOLE_T_PUTC] 34 adrp x1, console_\_driver\()_getc 35 add x1, x1, :lo12:console_\_driver\()_getc 36 str x1, [x0, #CONSOLE_T_GETC] 42 adrp x1, console_\_driver\()_flush 43 add x1, x1, :lo12:console_\_driver\()_flush 44 str x1, [x0, #CONSOLE_T_FLUSH] 49 mov x1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH) [all …]
/trusted-firmware-a/plat/nxp/soc-ls1028a/aarch64/
A D	ls1028a.S	261 lsl x1, x1, #8 296 orr x1, x1, #CPUECTLR_SMPEN_EN 302 bic x1, x1, #CPUECTLR_TIMER_MASK 395 orr x1, x1, #CNTP_CTL_EL0_IMASK 614 orr x1, x1, x2 618 orr x1, x1, x2 708 bic x1, x1, #CPUECTLR_RET_MASK 710 orr x1, x1, #CPUECTLR_SMPEN_EN 792 bic x1, x1, #CPUECTLR_RET_MASK 1147 orr x1, x1, #0x4 [all …]
/trusted-firmware-a/bl2/aarch64/
A D	bl2_entrypoint.S	23 mov x21, x1 50 orr x0, x0, x1 65 adr x1, __RW_END__ 66 sub x1, x1, x0 77 adrp x1, __BSS_END__ 78 add x1, x1, :lo12:__BSS_END__ 79 sub x1, x1, x0 85 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 86 add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__ 87 sub x1, x1, x0 [all …]
/trusted-firmware-a/drivers/coreboot/cbmem_console/aarch64/
A D	cbmem_console.S	38 str x0, [x1, #CONSOLE_T_BASE] 40 str w2, [x1, #CONSOLE_T_CBMC_SIZE] 41 mov x0, x1 56 ldr w2, [x1, #CONSOLE_T_CBMC_SIZE] 57 ldr x1, [x1, #CONSOLE_T_BASE] 58 add x1, x1, #8 /* keep address of body in x1 */ 60 ldr w16, [x1, #-4] /* load cursor (one u32 before body) */ 70 strb w0, [x1, w16, uxtw] /* body[cursor] = character */ 80 str w16, [x1, #-4] /* write back cursor to memory */ 94 ldr x1, [x0, #CONSOLE_T_CBMC_SIZE] [all …]
/trusted-firmware-a/plat/marvell/armada/common/
A D	mrvl_sip_svc.c	74 u_register_t x1, in mrvl_sip_smc_handler() argument 82 u_register_t ret, read, x5 = x1; in mrvl_sip_smc_handler() 86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler() 90 if (!is_cp_range_valid(&x1)) { in mrvl_sip_smc_handler() 92 __func__, smc_fid, x1); in mrvl_sip_smc_handler() 96 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; in mrvl_sip_smc_handler() 97 x1 += MVEBU_COMPHY_OFFSET; in mrvl_sip_smc_handler() 148 if (x1 >= MV_SIP_DFX_THERMAL_INIT && in mrvl_sip_smc_handler() 153 if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) { in mrvl_sip_smc_handler() 160 ret = mvebu_ddr_phy_write(x1, x2); in mrvl_sip_smc_handler() [all …]
/trusted-firmware-a/services/spd/trusty/
A D	trusty_helpers.S	40 ldr x2, [x1] 41 ldr x3, [x1, #0x08] 42 ldr x4, [x1, #0x10] 59 push x8, xzr, x1 60 push xzr, xzr, x1 61 push xzr, xzr, x1 62 push xzr, xzr, x1 63 push xzr, xzr, x1 64 push xzr, xzr, x1 66 push xzr, x9, x1 [all …]
/trusted-firmware-a/plat/arm/board/common/aarch64/
A D	board_arm_helpers.S	23 mrs x1, CurrentEl 24 lsr x1, x1, #MODE_EL_SHIFT 25 lsl x1, x1, #V2M_SYS_LED_EL_SHIFT 29 orr x0, x0, x1 30 mov x1, #V2M_SYSREGS_BASE 31 add x1, x1, #V2M_SYS_LED 32 str w0, [x1]
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A D	plat_trampoline.S	24 ldr x1, [x0] 28 cmp x1, x2 32 mov x1, #TEGRA194_STATE_SYSTEM_RESUME 33 lsl x1, x1, #16 35 add x1, x1, x2 36 str x1, [x0] 49 ldp x3, x4, [x1], #16 56 ldrb w3, [x1], #1 114 sub x0, x0, x1 128 sub x0, x0, x1 [all …]
/trusted-firmware-a/plat/mediatek/mt6795/aarch64/
A D	plat_helpers.S	35 mov_imm x1, 0xdead1abf 46 mrs x1, mpidr_el1 49 and x1, x1, #MPIDR_CLUSTER_MASK 51 add x1, x2, x1, LSR #6 60 add x2, x2, x1, LSL # 3 63 ldr x1, [x2] 67 strb w0, [x1] 69 add x1, x1, #1 71 str x1, [x2] 106 mov_imm x1, UART_CLOCK [all …]
/trusted-firmware-a/bl2u/aarch64/
A D	bl2u_entrypoint.S	21 mov x20, x1 45 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 47 orr x0, x0, x1 62 adr x1, __RW_END__ 63 sub x1, x1, x0 74 adrp x1, __BSS_END__ 75 add x1, x1, :lo12:__BSS_END__ 76 sub x1, x1, x0 104 mov x1, x21
/trusted-firmware-a/plat/renesas/common/aarch64/
A D	plat_helpers.S	93 cmp x1, #0x0008 95 cmp x1, #0x000c 107 cmp x1, #0 154 mov x1, #0x1 155 str x1, [x3] 236 cmp x0, x1 260 mov x1, sp 268 mov sp, x1 279 mov x1, sp 297 mov sp, x1 [all …]
/trusted-firmware-a/plat/arm/css/common/aarch64/
A D	css_helpers.S	40 ldr x1, [x0] 41 cbz x1, 1f 42 br x1 78 and x1, x0, #MPIDR_CPU_MASK 81 add x0, x1, x0, LSR #6 99 mov x1, #0xffffffff 100 cmp x0, x1 112 mov_imm x1, SCP_BOOT_CFG_ADDR 113 ldr x1, [x1] 114 ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ [all …]
/trusted-firmware-a/plat/arm/board/fvp/aarch64/
A D	fvp_helpers.S	41 mov_imm x1, PWRC_BASE 42 str w0, [x1, #PPOFFR_OFF] 58 ldr x1, [x0] 59 cbz x1, 1f 60 br x1 92 mov_imm x1, PWRC_BASE 93 str w2, [x1, #PSYSR_OFF] 94 ldr w2, [x1, #PSYSR_OFF] 136 and x0, x0, x1 173 madd x1, x2, x4, x1 [all …]

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Last Index update Sat Jun 03 09:59:21 CST 2023