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/trusted-firmware-a/plat/nxp/common/aarch64/
A Dbl31_data.S37 clz x2, x0
49 add x2, x2, x1
59 mul x2, x2, x0
73 sub x2, x2, x1
77 dc ivac, x2
97 clz x2, x0
109 add x2, x2, x1
119 mul x2, x2, x0
133 sub x2, x2, x1
255 sub x2, x3, x2
[all …]
/trusted-firmware-a/lib/compiler-rt/builtins/
A Dpopcountdi2.c22 du_int x2 = (du_int)a; in __popcountdi2() local
23 x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); in __popcountdi2()
25 x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); in __popcountdi2()
27 x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; in __popcountdi2()
29 su_int x = (su_int)(x2 + (x2 >> 32)); in __popcountdi2()
/trusted-firmware-a/plat/mediatek/mt6795/aarch64/
A Dplat_helpers.S24 adr x2, ptr_atf_crash_flag
25 ldr x2, [x2]
27 cbz x2, exit_putc
34 ldr x2, [x2]
37 str w1, [x2]
39 ldr w2, [x2]
51 add x1, x2, x1, LSR #6
54 ldr x2, [x2]
60 add x2, x2, x1, LSL # 3
63 ldr x1, [x2]
[all …]
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_trampoline.S25 mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
26 lsl x2, x2, #16
27 add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
28 cmp x1, x2
34 mov x2, #TEGRA194_STATE_SYSTEM_RESUME
35 add x1, x1, x2
43 ldr x2, [x2, #8]
47 cmp x2, #16
51 sub x2, x2, #16
55 cbz x2, boot_cpu
[all …]
/trusted-firmware-a/lib/extensions/amu/aarch64/
A Damu_helpers.S61 adr x2, 1f
76 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
78 br x2
137 adr x2, 1f
152 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
154 br x2
181 adr x2, 1f
200 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
202 br x2
291 br x2
[all …]
/trusted-firmware-a/lib/romlib/
A Dinit.s21 adrp x2, __DATA_RAM_END__
22 add x2, x2, :lo12:__DATA_RAM_END__
23 sub x2, x2, x0
29 adrp x2, __BSS_END__
30 add x2, x2, :lo12:__BSS_END__
31 sub x2, x2, x0
/trusted-firmware-a/plat/imx/common/
A Dimx_sip_svc.c21 u_register_t x2, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
39 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
41 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
44 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
47 return imx_otp_handler(smc_fid, handle, x1, x2); in imx_sip_handler()
49 SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
53 SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle)); in imx_sip_handler()
57 SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
A Dimx_sip_handler.c41 u_register_t x2, in imx_srtc_handler() argument
49 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
72 u_register_t x2, in imx_cpufreq_handler() argument
77 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
95 u_register_t x2, in imx_wakeup_src_handler() argument
115 u_register_t x2) in imx_otp_handler() argument
140 u_register_t x2, in imx_misc_set_temp_handler() argument
152 u_register_t x2, in imx_src_handler() argument
160 if (x2 != 0U) { in imx_src_handler()
206 u_register_t x2, in imx_buildinfo_handler() argument
[all …]
/trusted-firmware-a/plat/nxp/soc-ls1028a/aarch64/
A Dls1028a.S108 mov x2, x0
115 tst x0, x2
256 mov x2, #1
257 lsl x2, x2, x1
262 orr x2, x2, x1
265 orr x2, x2, #ICC_SGI0R_EL1_INTID
422 cmp x2, x3
522 add x2, x2, x4
523 dc cvac, x2
1337 sub x2, x2, #1
[all …]
/trusted-firmware-a/plat/st/stm32mp1/services/
A Dbsec_svc.c16 uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3, in bsec_main() argument
24 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
28 result = bsec_program_otp(x3, x2); in bsec_main()
32 result = bsec_write_otp(x3, x2); in bsec_main()
36 result = bsec_read_otp(&tmp_data, x2); in bsec_main()
41 result = bsec_shadow_register(x2); in bsec_main()
46 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
51 result = bsec_write_otp(tmp_data, x2); in bsec_main()
/trusted-firmware-a/plat/imx/common/include/
A Dimx_sip_svc.h38 u_register_t x2, u_register_t x3,
42 u_register_t x2, u_register_t x3);
47 u_register_t x2, u_register_t x3, void *handle);
52 u_register_t x2, u_register_t x3);
54 u_register_t x2, u_register_t x3, u_register_t x4);
56 u_register_t x2, u_register_t x3);
58 u_register_t x1, u_register_t x2);
60 u_register_t x2, u_register_t x3,
64 u_register_t x2, u_register_t x3,
/trusted-firmware-a/lib/cpus/aarch64/
A Dcpu_helpers.S41 cbz x2, 1f
44 br x2
67 cmp x0, x2
68 csel x2, x2, x0, hi
130 cbz x2, 1f
131 blr x2
158 mrs x2, midr_el1
208 cbz x2, error_exit
209 mov x2, #0
248 csel x0, x2, x3, ls
[all …]
A Ddenver.S167 cmp x1, x2
187 cmp x1, x2
195 lsl x2, x1, #16
201 lsr x2, x2, #32
203 and x2, x2, x1
204 cbnz x2, 1b
220 mov x2, #0x10000
221 and x1, x1, x2
258 mrs x2, vbar_el3
259 csel x0, x1, x2, ne
[all …]
A Dcpuamu_helpers.S45 adr x2, 1f
46 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
48 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
50 br x2
/trusted-firmware-a/plat/nvidia/tegra/soc/t210/
A Dplat_sip_calls.c43 uint64_t x2, in plat_sip_handler() argument
59 if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) in plat_sip_handler()
62 switch (x2) { in plat_sip_handler()
77 ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2); in plat_sip_handler()
86 val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); in plat_sip_handler()
89 mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); in plat_sip_handler()
/trusted-firmware-a/plat/marvell/armada/common/
A Dmrvl_sip_svc.c75 u_register_t x2, in mrvl_sip_smc_handler() argument
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
99 if (x2 >= MAX_LANE_NR) { in mrvl_sip_smc_handler()
101 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); in mrvl_sip_smc_handler()
119 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
123 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2); in mrvl_sip_smc_handler()
150 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
154 ret = mvebu_dfx_misc_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
[all …]
/trusted-firmware-a/plat/hisilicon/hikey/aarch64/
A Dhikey_helpers.S48 mov_imm x2, PL011_BAUDRATE
89 ldr x2, =0xf7020000
91 str w1, [x2, #4]
93 str w1, [x2, #8]
95 str w1, [x2, #16]
97 str w1, [x2, #32]
99 mrs x2, currentel
100 and x2, x2, #0xc0
102 cmp x2, #0x04
/trusted-firmware-a/plat/mediatek/common/
A Dmtk_sip_svc.c27 u_register_t x2, in mediatek_plat_sip_handler() argument
42 u_register_t x2, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
68 (uint32_t)x2); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
93 u_register_t x2, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/trusted-firmware-a/plat/hisilicon/hikey960/aarch64/
A Dhikey960_helpers.S52 mov_imm x2, PL011_BAUDRATE
93 ldr x2, =0xf7020000
95 str w1, [x2, #4]
97 str w1, [x2, #8]
99 str w1, [x2, #16]
101 str w1, [x2, #32]
103 mrs x2, currentel
104 and x2, x2, #0x0c
106 cmp x2, #0x04
/trusted-firmware-a/services/std_svc/
A Dstd_svc_setup.c81 u_register_t x2, in std_svc_smc_handler() argument
92 x2 &= UINT32_MAX; in std_svc_smc_handler()
116 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
134 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
145 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
152 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
159 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
169 return rmmd_gtsi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
176 return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
/trusted-firmware-a/plat/marvell/armada/a3k/common/
A Da3700_sip_svc.c31 u_register_t x2, in mrvl_sip_smc_handler() argument
41 __func__, smc_fid, x1, x2); in mrvl_sip_smc_handler()
45 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
54 ret = mvebu_3700_comphy_power_on(x1, x2); in mrvl_sip_smc_handler()
58 ret = mvebu_3700_comphy_power_off(x1, x2); in mrvl_sip_smc_handler()
62 ret = mvebu_3700_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
/trusted-firmware-a/lib/pmf/
A Dpmf_smc.c19 u_register_t x2, in pmf_smc_handler() argument
32 x2 = (uint32_t)x2; in pmf_smc_handler()
42 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
55 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
/trusted-firmware-a/lib/aarch64/
A Dmisc_helpers.S59 add x2, x0, x1
398 cmp x2, #16
402 sub x2, x2, #16
406 cbz x2, m_end
409 subs x2, x2, #1
520 adrp x2, __GOT_END__
521 add x2, x2, :lo12:__GOT_END__
542 cmp x1, x2
548 adrp x2, __RELA_END__
549 add x2, x2, :lo12:__RELA_END__
[all …]
/trusted-firmware-a/plat/nxp/soc-lx2160a/aarch64/
A Dlx2160a.S133 tst x0, x2
292 mov x2, #1
293 lsl x2, x2, x1
298 orr x2, x2, x1
301 orr x2, x2, #ICC_SGI0R_EL1_INTID
453 cmp x2, x3
546 add x2, x2, #RSTCNTL_OFFSET
547 dc cvac, x2
1769 cbz x2, 1f
1771 sub x2, x2, #1
[all …]
/trusted-firmware-a/bl31/aarch64/
A Dea_delegate.S67 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
113 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
174 ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH
175 cmp x2, #ERROR_STATUS_SET_UC
210 ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
211 cmp x2, #ERROR_STATUS_UET_UC
245 mrs x2, spsr_el3
247 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
266 mov x2, xzr
297 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
[all …]

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